ispLEVER Classic 软件

适用于莱迪思成熟的可编程FPGA和所有的CPLD和SPLD系列。

相关产品

ispLEVER Classic是针对莱迪思的CPLD和成熟的可编程产品的设计环境。它可以应用于莱迪思器件的整个设计过程，从概念设计到器件JEDEC或位流编程文件输出。ispLEVER Classic支持的可编程逻辑系列的详细信息如下。

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概述

当前版本是ispLEVER Classic 2.0，于2015年6月16日发布。

ispLEVER Classic软件支持Windows 7、Windows Vista和Windows XP操作系统。

若使用其它莱迪思FPGA系列产品进行设计，请下载Lattice Diamond或iCEcube2软件。您可同时安装并运行Lattice Diamond、iCEcube2和ispLEVER Classic软件。

下载和安装ispLEVER Classic软件

按照下面三个步骤来下载、安装ispLEVER Classic软件并获取许可证。

STEP1 - 下载

ispLEVER Classic包含以下模块：ipLEVER Classic基本安装模块（包含Synplify Synthesis模块和用于仿真的Aldec Active-HDL莱迪思版）、ispLEVER Classic FPGA安装模块。

点击下方链接下载软件安装包。

模块 支持的器件/特性
ispLEVER Classic 2.0 基本模块：
包含ispLEVER Project Navigator以及在您实现右侧列出的可编程产品系列设计时所需的所有工具和器件库，还包括了Synopsys®公司出品适用于HDL综合的Synplify™ Pro综合工具（I-2014.03LC）莱迪思版以及Aldec Active-HDL莱迪思II版仿真器9.3版。		 CPLD
ispMACH 4000ZE/Z/V/B/C
ispMACH 5000VG
ispMACH 5000B
ispMACH 4A3/5
MACH4/5
ispXPLD 5000MX
ispLSI 8000
ispLSI 5000VE
ispLSI 2000VE
ispLSI 1000

SPLD
GAL 和 ispGAL

GDX
ispGDXVA
ispGDX2
FPGA
ispXPGA
ispLEVER Classic 2.0 FPGA 模块：
本可选模块添加对ORCA FPGA和FPSC器件的支持。
请注意在安装本模块之前必须先安装基本模块。		 FPGA
ORCA FPGA
ORCA FPSC

STEP 2 - 安装每个ispLEVER Classic模块

首先从安装ispLEVER Classic基本模块开始：解压下载的文件，然后双击解压的文件并开始安装过程。您也可以下载安装指南，获得更详细的指导和选项说明。

对于Windows 10系统 — 请下载支持Windows 10的服务补丁。请按照下载安装包中的readme.txt文件的安装说明进行操作。

STEP 3 - 获取ispLEVER Classic许可证

您需要一个有效的许可证来运行ispLEVER Classic软件。请点击本页的许可证选项卡以申请一年期许可证。莱迪思将通过电子邮件将许可证发送给您。将邮件中的license.dat文件保存至软件安装目录<install_path>License文件夹中。之后即可运行ispLEVER Classic软件。

Licensing

STEP 3 - Purchase/Renew ispLEVER Classic License

The ispLEVER Classic license enables users to design and optimize solutions for CPLD and Legacy devices.

To purchase an ispLEVER Classic license, please go to the Online Store or contact a local sales representative or distributor.

If you have purchased a Software license and received a Software Serial Number, please go to our Subscription licensing form.

版本历史

ispLEVER Classic 2.1

  • Replaced Aldec™ Active-HDL™ with Mentor® ModelSim® Lattice FPGA Edition. Active-HDL Lattice Edition is still supported but not included.

ispLEVER Classic 2.0 版本

莱迪思综合引擎（LSE）

  • 添加对Mach4000 CPLD产品系列的支持。LSE可作为默认综合工具用于上述产品系列的相关项目。现有的项目可继续使用之前的综合工具。针对Mach4000 CPLD器件，用户可选择LSE或Synopsys Synplify Pro。

Aldec Active-HDL仿真工具升级至10.1版本

软件下载和文档

快速参考
技术资源
资讯资源
下载
标题 编号 版本 日期 格式 文件大小
选择全部
Generating a Schematic Symbol for OrCAD Capture
AN8075 9/1/2006 PDF 554.9 KB
Power Estimation in ispXPGA Devices (spreadsheet file)
This .zip contains the spreadsheet that is referenced in TN1043 		TN1043 5/1/2004 ZIP 31.8 KB
Power Estimation in ispXPGA Devices
Please note that a spreadsheet with built-in formulas is also available for use with TN1043, and available for download on this page. 		TN1043 1/1/2004 PDF 447.1 KB
标题 编号 版本 日期 格式 文件大小
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ispLEVER Classic 2.1 Installation Guide
2.1 12/30/2020 PDF 539.8 KB
标题 编号 版本 日期 格式 文件大小
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ABEL Design Manual
(ispLEVER 4.x, 5.x, 6.x, Classic) 		3/1/2003 PDF 606.2 KB
ABEL-HDL Reference Manual
(ispLEVER 4.x, 5.x, 6.x, Classic) 		3/1/2003 PDF 1.4 MB
LSE for ispLEVER Classic User Guide
1.0 6/16/2015 PDF 245.7 KB
ispLSI Macro Library Reference Manual
Contains functional and pin descriptions of the schematic macros available in ispLEVER. (ispLEVER 4.x, 5.x, 6.x, Classic) 		8/1/2000 PDF 3.3 MB
FPGA Physical Design Rule Check (DRC) Desk Reference
Contains descriptions of design rule check warning and error messages you may encounter when running your FPGA designs in ispLEVER's Project Navigator. (ispLEVER 4.x, 5.x, 6.x, 7.x, 8.x) 		8.0 11/10/2009 PDF 102.9 KB
Generic Macro Library Reference Guide
Contains functional and pin descriptions of the schematic "generic" macros available in ispLEVER Classic. Macros are compatible with ispMACH 4000 Family CPLDs. 		3/5/2018 PDF 132.3 KB
FPGA Design Guide
Includes comprehensive instructions on how to use the ispLEVER tools to design for Lattice FPGAs. (ispLEVER 8.0) 		8.0 11/10/2009 PDF 2.5 MB
Simulating Designs for Lattice FPGA Devices
This document explains how to use Synopsys® VCS®, Cadence® NCVerilog®, Cadence NC-VHDL®, and Aldec Riviera Pro® and Active-HDL® software to simulate designs that target Lattice Semiconductor FPGAs. (ispLEVER 6.x, 7.x) 		6/15/2007 PDF 111.5 KB
Schematic Entry Reference Manual
(ispLEVER Classic) 		11/24/2004 PDF 698 KB
标题 编号 版本 日期 格式 文件大小
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PCN10A-11 Notification of Intent to Freeze ispLEVER After Version 8.2
Conversion 		PCN10A-11 1.0 7/25/2011 PDF 52.7 KB
标题 编号 版本 日期 格式 文件大小
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.8 10/13/2025 ZIP 3 MB
标题 编号 版本 日期 格式 文件大小
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Synthesis Data Flow Tutorial
This tutorial shows you how to use Synplicity Synplify® Pro for Lattice with ispLEVER® to synthesize a Verilog HDL design and to generate an EDIF file for a Lattice FPGA device. Tutorial Topics/Tools: FPGA logic synthesis, ispLEVER, Synplify. 		12/15/2008 PDF 314.3 KB
Using the ispXPGA Floorplanner
How to use the Floorplanner to locate elements, make pin and block assignments, and examine timing delay in a design targeted to an ispXPGA device. Tutorial Topics/Tools: Design Planning, ispLEVER, Floorplanner. (ispLEVER 4.x, 5.x, 6.x, Classic) 		5/1/2005 PDF 515.7 KB
Schematic and ABEL-HDL Design
How to design, simulate, implement, and verify a counter circuit targeted to a CPLD device. The design uses a top-level schematic and two lower-level ABEL-HDL modules. Tutorial Topics/Tools: CPLD Schematic and HDL Design Entry, CPLD Fitting, ispLEVER 		5/1/2006 PDF 2 MB
LSE for ispLEVER Classic 2.0 Tutorial
1.0 6/16/2015 PDF 372.7 KB
HDL Synthesis Design with LeonardoSpectrum: CPLD Flow
How to use LeonardoSpectrum to synthesize a Verilog design for a Lattice CPLD device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, LeonardoSpectrum. (ispLEVER 4.x, 5.x, 6.x) 		5/1/2005 PDF 313 KB
HDL Synthesis Design with Synplify: CPLD Flow
How to use Synplify to synthesize a VHDL design for a Lattice CPLD device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, Synplify (ispLEVER 6.x) 		5/1/2005 PDF 446.1 KB
HDL Synthesis Design with LeonardoSpectrum: ispXPGA Flow
How to use LeonardoSpectrum to synthesize a Verilog design for a Lattice ispXPGA device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, LeonardoSpectrum. (ispLEVER 4.x, 5.x, 6.x) 		5/1/2005 PDF 363.7 KB
HDL Synthesis Design with Precision RTL: CPLD Flow
This tutorial shows you how to use Mentor Graphics Precision RTL Synthesis from within ispLEVER to synthesize a Verilog design and generate an EDIF file for a Lattice CPLD device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, Precision RTL 		5/1/2006 PDF 263.8 KB
HDL Synthesis Design with Synplify: ispXPGA Flow
How to use Synplify to synthesize a VHDL design for a Lattice ispXPGA device. Tutorial Topics/Tools: Logic Synthesis, ispLEVER, Synplify. 		5/1/2005 PDF 509.1 KB
标题 编号 版本 日期 格式 文件大小
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Active-HDL simulation libraries for ispLEVER Classic devices
Use these libraries if you wish to use ispLEVER Classic with Active-HDL Lattice Edition. 		10/19/2011 ZIP 81.6 MB
ispLEVER Classic 2.1 Service Pack for Windows 10
1.0 12/30/2020 ZIP 18.1 MB
ispLEVER Classic 2.1 FPGA Module
2.1 12/30/2020 ZIP 350.8 MB
ispLEVER Classic 2.1 Base Module
2.1 12/30/2020 ZIP 786.8 MB
PALtoGAL v3 12
Translates PAL JEDEC files to GAL JEDEC format. 		5/24/2001 ZIP 35.4 KB

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