MachXO5™-NX

Advanced Secure Control FPGA

MachXO5-NX is Lattice’s secure control FPGA product family. Known for features such as embedded flash, high I/O, and best-in-class security, Lattice’s secure control FPGAs are widely used for system control and management applications in the Compute, Communications, and Industrial market segments. MachXO5-NX improves upon previous generations with higher logic density, faster interfaces, larger internal memory, and enhanced security features enabling more complex board management designs.

Lattice MachXO5-NX™ TDQ devices, built on Lattice’s low power Nexus platform, expand the MachXO5™-NX FPGA family’s capabilities for secure control applications with root-of-trust features supporting state-of-the art  classical cryptography and CNSA2.0 approved Post-Quantum Cryptography (PQC) to address the increased threat to system security. With full suite of CNSA2.0 prescribed PQC algorithm support, these devices ensure robust protection against emerging quantum threats, future-proofing your security infrastructure.

Higher Density, More Memory for Complex Control Applications – Up to 100K logic density, 7.3Mb internal memory , and 55Mb dedicated user flash memory (UFM).

Fast and Proven I/O Capabilities – Consistent robust I/O operation as previous generation, 1.0V I/O supporting modern CPU, high speed LVDS, MIPI and PCIe interfaces.

Device Security Protects Intellectual Property – Root-of-Trust hardware solutions with internal flash configuration, AES256 bitstream encryption, up to ECDSA-521 and RSA4K bitstream authentication, configuration port lock, and run-time security.

Extended density range and features available in the Mach XO5-NX family.

Features

  • 15K, 25K, 35K, 65K, 55K and 100K logic cell density and up to 378 I/O pins. MachXO5-NX devices (35K, 65K, 55K and 100K LC) support PCIe Gen2.
  • Up to 55 Mbits of dedicated user flash memory (UFM) and on-chip multi-boot configuration
  • Secure FPGA design using ECDSA-256/384/521 bitstream authentication and AES256 bitstream encryption
  • Low power, high reliability, and support for ADC and DSP on the Lattice Nexus™ Platform
  • Full suite of CNSA2.0 required and NIST-approved algorithms (LMS, XMSS, ML-DSA, ML-KEM, SLH-DSA, AES256, SHA2, SHA3, SHAKE)

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Family Table

MachXO5-NX Device Selection Guide
  MachXO5-NX MachXO5D-NX MachXO5-NX TD/TDQ
Features LFMXO5-25 LFMXO5-55T LFMXO5-100T LFMXO5-35/T LFMXO5-65/T LFMXO5-15D LFMXO5-55TD LFMXO5-55TDQ LFMXO5-20TD
LFMXO5-20TDQ
LFMXO5-30TD
LFMXO5-30TDQ
Logic Cells 27k 53k 96k 35k 65k 14k 53k 38K 20K 30K
Embedded Memory
(EBR) Blocks (18 kb)
80 166 208 208 128 20 64 39 42 46
Embedded Memory
(EBR) Bits (kb)
1440 2988 3744 1890 2304 360 2988 342 756 828
Distributed RAM
Bits (kb)
184 320 639 260 300 95 320 248 122 190
Large Memory
(LRAM) Blocks
1 5 7 1 2 1 5 5 1 1
Large Memory
(LRAM) Bits (kb)
512 2560 3584 512 1024 512 2560 2560 512 512
18 X 18
Multipliers
20 146 156 48 128 16 110 93 48 48
ADC Blocks 2 2 2 1 1 2 2 2 1 1
PCIe Gen2
hard IP
0 1 1 1 1 0 1 1 1 1
GPLL 2 4 4 2 2 2 4 4 2 2
UFM* (kb) 14848 79872 79872 21504 21504 8160 14880 14880 16320 16320
Bitstream
Authentication
ECDSA-256 ECDSA-256 ECDSA-256 ECDSA-256 ECDSA-256 ECDSA-384 ECDSA-384/521
,RSA-3K/4K
ECDSA-384/521
,XMSS/LMS,
ML-DSA
ECDSA-384
XMSS/LMS**
ECDSA-384
XMSS/LMS**
Highest Classic
Crypto services
SHA/HMAC-256
,TRNG
SHA/HMAC-256
,TRNG
SHA/HMAC-256
,TRNG
SHA/HMAC-256
,TRNG
SHA/HMAC-256
,TRNG
AES-256,
ECDSA-384,
SHA/HMAC-384
,TRNG
AES-256,
ECDSA-521,
SHA/HMAC-512
,TRNG
AES-256,
ECDSA-521,
SHA/HMAC-512
,TRNG
AES-256
,ECDSA-384,
SHA/HMAC-512
,TRNG
AES-256,
ECDSA-384,
SHA/HMAC-512
,TRNG
Highest PQC
Crypto Services(**)
XMSS/LMS,
ML-DSA,
ML-KEM
XMSS/LMS** XMSS/LMS**

*Without memory initialization
**PQC services available only in TDQ devices

   
0.8 mm Pitch Packages & SERDES/Total I/O (Wide Range GPIO+ High Performance GPIOs+ Dedicated ADC pins)
LFMXO5-25 LFMXO5-55T LFMXO5-100T LFMXO5-35/T LFMXO5-65/T LFMXO5-15D LFMXO5-55TD LFMXO5-55TDQ LFMXO5-20TD
LFMXO5-20TDQ
LFMXO5-30TD
LFMXO5-30TDQ
256 BBG
( 14 mm × 14 mm,
0.8 mm )
0/205
(159+40+6)
- - 1/173
(137+30+6)
1/173
(137+30+6)
0/205
(159+49+6)
- 1/170
(134+30+6)
1/170
(134+30+6)
400 BBG
( 17 mm × 17 mm,
0.8 mm )
0/305
(251+48+6)
2/297
(159+132+6)
2/297
(159+132+6)
0/318
(264+48+6)
0/318
(264+48+6)
0/305
(251+48+6)
2/297
(159+132+6)
2/297
(159+132+6)
0/315
(261+48+6)
0/315
(261+48+6)
484 BGA
( 19 mm × 19 mm,
0.8 mm )
1/371
(317+48+6)
1/371
(317+48+6)
1/368
(314+48+6)
1/368
(314+48+6)

Block Diagram

MachXO5-NX

  • Up to 100K logic cells, 7.3Mb embedded memory , and 55Mb dedicated user flash memory (UFM)
  • MachXO5T devices (35K,65K,55K & 100K LC) support PCIe Gen2 and LPDDR4
  • Up to 378 programmable I/O supporting 1.0/1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Protects intellectual property with bitstream encryption and authentication

Example Applications

Application – Network Switch

  • Aggregates control signals over PCIe
  • Offload real-time monitoring and management of SFPs from network CPU

Application – Hardware Management

  • Easily integrate hardware management functions into MachXO5-NX and L-ASC10
  • High I/O and multiple voltage level support simplify I/O bridging and expansion

Application – LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module

  • Supports LVDS Tunneling Protocol & Interface (LTPI) to aggregate low-speed serial interfaces
  • Enables server architecture that uses secure control modules
  • LTPI is also supported by MachXO3, MachXO3D and Mach-NX

Videos

AMI Firmware Security with the Lattice MachXO5D™ and AMI Tektagon Platform RoT

AMI Firmware Security with the Lattice MachXO5D™ and AMI Tektagon Platform RoT

AMI is showcasing a preview of the post-quantum capable Lattice MachXO5D™ Hardware Root of Trust controller, supporting the AMI Tektagon Platform Root of Trust solution. Delivering the most advanced firmware security to date, AMI Tektagon with the Lattice MachXO5D includes Intel PFR 4.0 compliance and supports CNSA 2.0 encryption, addressing the needs for post-quantum platform protection. This demonstration of a fully integrated silicon-firmware platform will feature PFR-compliant system firmware attestation and recovery from corruption.
Fidus Systems Video Streaming over LTPI (LVDS Tunneling Protocol and Interface)

Fidus Systems Video Streaming over LTPI (LVDS Tunneling Protocol and Interface)

The Open Compute Project has included the “LVDS Tunneling Protocol & Interface Specification” (LTPI) in the DC-SCM 2 Specification. Featuring Lattice’s LTPI IP running on Lattice MachXO5™-NX hardware, Fidus’ LTPI demo showcases the ease, value, and capabilities of a Lattice-based LTPI solution. The demonstration highlights the tunneling of various standard protocols and the creative utilization of the OEM/Data Channels, all while operating at maximum speed.
Intel Lincoln City Reference Architecture with Lattice FPGAs

Intel Lincoln City Reference Architecture with Lattice FPGAs

This demonstration showcases the Intel Lincoln City Reference Architecture, which incorporates 6 Lattice FPGAs. Designed as an Intel® Birch Stream-AP 1S Cloud Product Reference, it features Intel® 4.0 Platform Firmware Resiliency (PFR) using the Lattice Mach-NX device.
XMSS and LMS Digital-Signature System

XMSS and LMS Digital-Signature System

This demonstration features the Lattice MachXO3D™ and PQShield’s PQCryptolib, embedded to implement a secure boot based on LMS (Leighton-Micali Signature) and XMSS (eXtended Merkle Signature Scheme). This setup ensures robust security for embedded systems.

Design Resources

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当社の開発キットとボードで設計プロセスの合理化

IP & リファレンスデザイン

事前検証済み、開発期間を短縮

開発ソフトウェア

使いやすく、開発に必要な機能を提供

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5D-NX Secure Device Overview and Security Checklist
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02332 1.3 4/22/2025 WEB
MachXO5-NX Family Root-of-Trust Devices Data Sheet
FPGA-DS-02120 1.2 10/13/2025 PDF 3.5 MB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
Package Diagrams
FPGA-DS-02053 8.5 8/5/2025 PDF 9.4 MB
MachXO5-NX-Hardware-Checklist
FPGA-TN-02274 1.7 7/15/2025 PDF 1.2 MB
MachXO5-NX 25 Pinout
FPGA-SC-02038 1.0 5/26/2023 CSV 16.9 KB
MachXO5-NX High Speed IO Interface
FPGA-TN-02286 1.1 10/13/2025 PDF 3.7 MB
MachXO5-NX Family Data Sheet
FPGA-DS-02102 2.1 7/29/2025 PDF 4.1 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 2.5 10/13/2025 PDF 2.2 MB
MachXO5-NX 55T Pinout
FPGA-SC-02048 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 100T Pinout
FPGA-SC-02049 1.1 3/6/2024 CSV 16 KB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.8 10/1/2025 PDF 2 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.4 8/21/2024 PDF 3.5 MB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-02341 1.2 6/26/2025 PDF 568.1 KB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.7 6/26/2024 PDF 1.3 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 2.8 10/13/2025 PDF 820.9 KB
MachXO5-NX-Family Root-of-Trust Devices Hardware Checklist
FPGA-TN-02371 1.0 6/26/2024 PDF 670.7 KB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
ADC User Guide for Nexus Platform
FPGA-TN-02129 2.1 10/13/2025 PDF 1.3 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.7 10/13/2025 PDF 1.1 MB
Using TraceID
FPGA-TN-02084 2.8 4/15/2025 PDF 493.8 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.5 3/6/2025 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX Family Root-of-Trust Devices Data Sheet
FPGA-DS-02120 1.2 10/13/2025 PDF 3.5 MB
MachXO5-NX Family Data Sheet
FPGA-DS-02102 2.1 7/29/2025 PDF 4.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX Root-of-Trust Device Provisioning User Guide
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02333 0.84 4/22/2025 WEB
Embedded Security and Function Block with Advanced Key Management for MachXO5-NX (55TD) Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02353 1.0 4/22/2025 WEB
MachXO5D-NX Secure Device Overview and Security Checklist
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02332 1.3 4/22/2025 WEB
Embedded Security and Function Block User Guide for MachXO5-NX (15D) Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02320 1.4 9/23/2025 WEB
MachXO5-NX Secure Lock Policy Editor and Settings User Guide
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02326 0.80 6/26/2024 WEB
Advanced Key Management User Guide for MachXO5-NX (15D) Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions.
FPGA-TN-02321 1.2 9/23/2025 WEB
Signing JEDEC with HSM-Generated Signature
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6848 for detail instruction
FPGA-TN-02260 1.1 3/15/2025 WEB
Advanced Configuration Security Usage Guide for Nexus Platform
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6848 for detail instruction
FPGA-TN-02176 2.1 9/23/2025 WEB
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
MachXO5-NX-Hardware-Checklist
FPGA-TN-02274 1.7 7/15/2025 PDF 1.2 MB
MachXO5-NX High Speed IO Interface
FPGA-TN-02286 1.1 10/13/2025 PDF 3.7 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 2.5 10/13/2025 PDF 2.2 MB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.8 10/1/2025 PDF 2 MB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-02081 1.1 8/27/2024 PDF 2.6 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.4 8/21/2024 PDF 3.5 MB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-02341 1.2 6/26/2025 PDF 568.1 KB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.7 10/13/2025 PDF 1.9 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.7 6/26/2024 PDF 1.3 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 2.8 10/13/2025 PDF 820.9 KB
MachXO5-NX-Family Root-of-Trust Devices Hardware Checklist
FPGA-TN-02371 1.0 6/26/2024 PDF 670.7 KB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
Adding Scalable Power and Thermal Management to Nexus FPGAs
FPGA-AN-02079 1.0 1/31/2024 PDF 1.3 MB
ADC User Guide for Nexus Platform
FPGA-TN-02129 2.1 10/13/2025 PDF 1.3 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 5.1 8/5/2025 PDF 693.7 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.7 10/13/2025 PDF 1.1 MB
Using TraceID
FPGA-TN-02084 2.8 4/15/2025 PDF 493.8 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.5 3/6/2025 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Package Diagrams
FPGA-DS-02053 8.5 8/5/2025 PDF 9.4 MB
MachXO5-NX 25 Pinout
FPGA-SC-02038 1.0 5/26/2023 CSV 16.9 KB
MachXO5-NX 55T Pinout
FPGA-SC-02048 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 100T Pinout
FPGA-SC-02049 1.1 3/6/2024 CSV 16 KB
MachXO5-NX-20TD Pinout Table
FPGA-SC-02104 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX-30TD Pinout Table
FPGA-SC-02106 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX-20TDQ Pinout Table
FPGA-SC-02105 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX-55TDQ Pinout Table
FPGA-SC-02109 1.0 10/13/2025 CSV 15.9 KB
MachXO5-NX-30TDQ Pinout Table
FPGA-SC-02107 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX 55TD Pinout Table
FPGA-SC-02041 1.0 10/13/2025 CSV 16.3 KB
MachXO5-NX 15D-Pinout
FPGA-SC-02043 1.1 8/27/2025 CSV 16.1 KB
MachXO5-NX 65/T Pinout
FPGA-SC-02074 0.83 7/15/2025 CSV 21.4 KB
MachXO5-NX 35/T Pinout
FPGA-SC-02073 0.83 7/15/2025 CSV 21.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Advanced Key Management User Guide for MachXO5-NX
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instruction.
2/21/2024 WEB
Embedded Security and Function Block User Guide for MachXO5-NX Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instruction.
2/21/2024 WEB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.7 10/13/2025 PDF 1.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Design Advisory for Nexus LVDS-based SGMII
FPGA-DA250601 1.0 6/3/2025 PDF 77.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-02005 8.8 10/13/2025 ZIP 3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Future-Proof Trust: Securing Digital Systems with Lattice RoT FPGAs and Complete CNSA 2.0 Algorithm Coverage
WP0047 1.0 10/13/2025 PDF 2.5 MB
DC-SCM Implementation in Lattice FPGA
WP0031 2.0 3/22/2023 PDF 587.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[BSDL] LFMXO5-65T
FPGA-MD-02119 0.80 8/27/2025
[BSDL] LFMXO5-35T
FPGA-MD-02118 0.80 8/27/2025
[BSDL] LFMXO5-15D
FPGA-MD-02120 1.0 9/9/2025
[BSDL] LFMXO5-100
FPGA-MD-02043 1.14 4/18/2023 BSM 63.4 KB
[BSDL] LFMXO5-25
FPGA-MD-02027 1.14 5/31/2022 ZIP 18.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX Device Family Delphi Models
FPGA-MD-02031 1.5 10/13/2025 ZIP 45.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX IBIS Model file
FPGA-MD-02035 1.4 10/14/2025 ZIP 16.4 MB
[IBIS] MachXO5-NX
FPGA-MD-02035 1.3 7/15/2025 ZIP 16.1 MB

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