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I am migrating from one LatticeECP3 device/package to another LatticeECP3 device/package. Is there a…
157
LatticeECP3
Inquiries
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Diamond: What are the different factors that affect device speed, temperature and voltage selection…
1587
All FPGA
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1535
Platform Manager
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Diamond / LSFR: When implementing the Linear Feedback Shift Register (LFSR) Arithmetic Module in…
1534
All FPGA
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All FPGAs: What is an .elf file in LatticeMico8 Mico System Builder (MSB)?
1536
All FPGA
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Mico8 Microcontroller
ispMACH4000ZE: Do the oscillator or timer outputs consume macrocell logic in the ispMACH4000ZE…
151
ispMACH 4000
Architecture
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LatticeECP3: Does Lattice have a demo package integrating the CPRI core with an Ethernet MAC, HDLC…
1515
LatticeECP3
Lattice IP/Reference Design
CPRI
LatticeECP3: Why is the SERDES Quad C powered by VCCIB instead of supplying 1.2v, or 1.5v with…
1527
LatticeECP3
Lattice Evaluation Board
ECP3-Video Protocol
LatticeSC/M: What effect does a PCS local/remote fault signal to the 10Gb+ Ethernet MAC have on…
1514
All FPGA
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10Gb+ Ethernet MAC
What is the recommended setting for PLL_LOL_SET?
1577
LatticeECP2/M
Architecture
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Diamond: How does user run post-route simulations for multiple devices?
1579
All Devices
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LatticeECP3: Where is the reference design for SGMII to (G)MII bridge specified in IPUG60 ?
1524
LatticeECP3
Lattice IP/Reference Design
SGMII
How do MachXO2 dual-function output pins behave during configuration mode?
1574
MachXO2
Architecture
Configuration/Programming
DDR2: Is a new read pulse required per Burst (4 clock cycles) or only when the read sequence has…
1578
LatticeECP3
Architecture
DDR Memory Interface
ispLEVER / ispVM System: Why does it take 4 minutes to program the XP2 FPGA device with the svf file…
1501
LatticeXP2
Device Programming
Configuration/Programming
LatticeXP2: Can I configure LatticeMico32 to run my application after the FPGA is configured, and…
1597
LatticeXP2
Lattice IP/Reference Design
LatticeMico32
PAC Designer: Why do the post-fit equations differ from my design equations using PAC-Designer?
1590
Power Manager II
PAC-Designer
Compile/Fit
Diamond / LatticeECP3: What is the guideline to use a general routing based clock for the…
1591
LatticeECP3
Implementation
Timing Closure
How much duty cycle variation will a clock signal have at an output IO?
1592
All Devices
Customer Board Design
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LatticeECP3: Why are the LVDS input terminations modeled as resistors to 1.25v in the IBIS model…
1561
LatticeECP3
Device Modeling
IBIS
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