MachXO5™-NX

高级安全控制FPGA

相关产品

相关应用

MachXO5-NX是莱迪思的第五代安全控制FPGA产品系列。莱迪思的安全控制FPGA拥有嵌入式闪存、高速I/O和行业领先的安全性，广泛应用于计算、通信和工业市场的系统控制和管理应用。MachXO5-NX在前几代产品的基础上进行了升级，拥有更高的逻辑密度、更快的接口、更大的内部存储空间和更强大的安全功能，可实现更复杂的电路板管理设计。

更高的密度、更多存储空间实现复杂的控制应用——最高100K逻辑密度、7.3 Mb嵌入式存储器和55 Mb用户闪存。

高速可靠的IO功能——一贯稳健的I/O操作，1.0 V I/O支持当今的CPU、高速LVDS和MIPI接口。

器件安全保护知识产权——拥有内部闪存配置、AES256位流加密、最高ECDSA-521和RSA4K位流验证、配置端口锁定和运行时安全（Run-time security）的硬件可信根解决方案。

Mach XO5-NX系列现已推出新器件，带来更多密度范围和特性选择。

特性

  • 可选15K、25K、35K、55K、65K和100K逻辑密度和多达378个I/O引脚
  • MachXO5-NX器件（35K、65K、55K和100K LC）支持PCIe Gen2
  • 最多55 Mb专用用户闪存，支持片上多重引导配置
  • 使用ECDSA-256/384/521位流认证和AES256位流加密保障FPGA设计安全
  • Lattice Nexus™平台的低功耗、高稳定性和对ADC和DSP的支持

跳转到

产品系列表

MachXO5-NX器件选型指南
    MachXO5T-NX MachXO5D-NX
特性 LFMXO5-25 LFMXO5-55T LFMXO5-100T LFMXO5-15D LFMXO5-55TD
逻辑单元
 25k
 53k 96k 14k 53k
嵌入式存储器（EBR）块（18 kb） 80 166 208 20 166
嵌入式存储器（EBR）位（kb） 1440 2988 3744 360 2988
分布式RAM位（kb） 184 320 639 95 320
大型存储器（LRAM）块 1 5 7 1 5
大型存储器（LRAM）位（kb） 512 2560 3584 512 2560
18 X 18乘法器 20 146 156 16 146
ADC模块 2 2 2 2 2
450 MHz高频振荡器 1 1 1 1 1
128 kHz低频振荡器 1 1 1 1 1
PCIe Gen2硬核IP 0 1 1 0 1
GPLL 2 4 4 2 4
UFM* (kb) 15360 79872 79872 13312 72192
位流验证 ECDSA-256 ECDSA-256 ECDSA-256 ECDSA-384 ECDSA-521

*未初始化存储

0.8 mm引脚封装 & SERDES/I/O总数（宽范围GPIO/高性能GPIO）/专用ADC引脚

LFMXO5-25 LFMXO5-55T LFMXO5-100T LFMXO5-15D LFMXO5-55TD
256 BBG (14 mm × 14 mm, 0.8 mm) 0 / 199 (159/40) / 6 - - 0 / 199 (159/40) / 6 -
400 BBG (17 mm × 17 mm, 0.8 mm) 0 / 299 (251/48) / 6 2 / 291 (159/132) / 6 2 / 291 (159/132) / 6 0 / 299 (251/48) / 6 2 / 291 (159/132) / 6

框图

MachXO5-NX-100T Block Diagram放大图片

MachXO5-NX

  • 多达100K逻辑单元、7.3 Mb存储器和55 Mb专用用户闪存
  • MachXO5T器件（35K、65K、55K & 100K LC）支持PCIe Gen2和LPDDR4
  • 多达378个可编程I/O，支持1.0/1.2/1.5/1.8/2.5/3.3 I/O电压
  • 通过位流加密和身份验证保护IP

应用示例

Block Diagram - Application - Network Switch放大图片

应用 – 网络交换机

  • 通过PCIe汇聚控制信号
  • 分担网络CPU的SFP实时监控和管理功能
Application – Hardware Management放大图片

应用：硬件管理

  • 轻松地将硬件管理功能集成到MachXO5-NX和L-ASC10中
  • 支持高速IO和多种电压电平，简化IO桥接和拓展
Application – LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module 放大图片

应用：DC-SCM中的LVDS通道协议和接口（LTPI）

  • 支持LVDS通道协议和接口（LTPI），聚合低速串行接口
  • 实现使用安全控制模块的服务器架构
  • MachXO3、MachXO3D和Mach-NX也支持LTPI

视频

AMI Firmware Security with the Lattice MachXO5D™ and AMI Tektagon Platform RoT

使用莱迪思MachXO5D™和AMI Tektagon平台RoT的AMI固件安全性

AMI展示了具有后量子加密功能的莱迪思MachXO5D™硬件可信根控制器的预览版本，它支持AMI Tektagon平台可信根解决方案。采用莱迪思MachXO5D的AMI Tektagon提供了迄今为止最先进的固件安全性，包括英特尔PFR 4.0合规和支持CNSA 2.0加密，满足了后量子平台保护的需求。这个充分集成的芯片固件平台演示将具有符合PFR标准的系统固件验证和损坏恢复功能。
Fidus Systems Video Streaming over LTPI (LVDS Tunneling Protocol and Interface)

Fidus Systems Video Streaming over LTPI (LVDS Tunneling Protocol and Interface)

The Open Compute Project has included the “LVDS Tunneling Protocol & Interface Specification” (LTPI) in the DC-SCM 2 Specification. Featuring Lattice’s LTPI IP running on Lattice MachXO5™-NX hardware, Fidus’ LTPI demo showcases the ease, value, and capabilities of a Lattice-based LTPI solution. The demonstration highlights the tunneling of various standard protocols and the creative utilization of the OEM/Data Channels, all while operating at maximum speed.
Intel Lincoln City Reference Architecture with Lattice FPGAs

Intel Lincoln City Reference Architecture with Lattice FPGAs

This demonstration showcases the Intel Lincoln City Reference Architecture, which incorporates 6 Lattice FPGAs. Designed as an Intel® Birch Stream-AP 1S Cloud Product Reference, it features Intel® 4.0 Platform Firmware Resiliency (PFR) using the Lattice Mach-NX device.
XMSS and LMS Digital-Signature System

XMSS and LMS Digital-Signature System

This demonstration features the Lattice MachXO3D™ and PQShield’s PQCryptolib, embedded to implement a secure boot based on LMS (Leighton-Micali Signature) and XMSS (eXtended Merkle Signature Scheme). This setup ensures robust security for embedded systems.

设计资源

开发套件和开发板

我们的开发板和开发套件能够简化您的设计流程

IP和参考设计

使用经过预先测试、可重复使用的功能简化您的设计工作

软件

覆盖整个设计流程，非常易于使用

文档

快速参考
技术资源
资讯资源
下载
标题 编号 版本 日期 格式 文件大小
选择全部
MachXO5D-NX Secure Device Overview and Security Checklist
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02332 1.3 4/22/2025 WEB
MachXO5-NX Family Root-of-Trust Devices Data Sheet
FPGA-DS-02120 1.2 10/13/2025 PDF 3.5 MB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
Package Diagrams
FPGA-DS-02053 8.5 8/5/2025 PDF 9.4 MB
MachXO5-NX-Hardware-Checklist
FPGA-TN-02274 1.7 7/15/2025 PDF 1.2 MB
MachXO5-NX High Speed IO Interface
FPGA-TN-02286 1.1 10/13/2025 PDF 3.7 MB
MachXO5-NX 25 Pinout
FPGA-SC-02038 1.0 5/26/2023 CSV 16.9 KB
MachXO5-NX Family Data Sheet
FPGA-DS-02102 2.1 7/29/2025 PDF 4.1 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 2.5 10/13/2025 PDF 2.2 MB
MachXO5-NX 55T Pinout
FPGA-SC-02048 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 100T Pinout
FPGA-SC-02049 1.1 3/6/2024 CSV 16 KB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.8 10/1/2025 PDF 2 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.4 8/21/2024 PDF 3.5 MB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-02341 1.2 6/26/2025 PDF 568.1 KB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 2.8 10/13/2025 PDF 820.9 KB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
ADC User Guide for Nexus Platform
FPGA-TN-02129 2.1 10/13/2025 PDF 1.3 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.7 6/26/2024 PDF 1.3 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.7 10/13/2025 PDF 1.1 MB
Using TraceID
FPGA-TN-02084 2.8 4/15/2025 PDF 493.8 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.5 3/6/2025 PDF 1.6 MB
MachXO5-NX-Family Root-of-Trust Devices Hardware Checklist
FPGA-TN-02371 1.0 6/26/2024 PDF 670.7 KB
标题 编号 版本 日期 格式 文件大小
选择全部
MachXO5-NX Family Root-of-Trust Devices Data Sheet
FPGA-DS-02120 1.2 10/13/2025 PDF 3.5 MB
MachXO5-NX Family Data Sheet
FPGA-DS-02102 2.1 7/29/2025 PDF 4.1 MB
标题 编号 版本 日期 格式 文件大小
选择全部
Embedded Security and Function Block User Guide for MachXO5-NX (15D) Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02320 1.4 9/23/2025 WEB
MachXO5-NX Secure Lock Policy Editor and Settings User Guide
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02326 0.80 6/26/2024 WEB
Advanced Key Management User Guide for MachXO5-NX (15D) Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02321 1.2 9/23/2025 WEB
Signing JEDEC with HSM-Generated Signature
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6848 for detail instruction 		FPGA-TN-02260 1.1 3/15/2025 WEB
Advanced Configuration Security Usage Guide for Nexus Platform
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6848 for detail instruction 		FPGA-TN-02176 2.1 9/23/2025 WEB
Embedded Security and Function Block with Advanced Key Management for MachXO5-NX (55TD) Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02353 1.0 4/22/2025 WEB
MachXO5-NX Root-of-Trust Device Provisioning User Guide
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02333 0.84 4/22/2025 WEB
MachXO5D-NX Secure Device Overview and Security Checklist
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instructions. 		FPGA-TN-02332 1.3 4/22/2025 WEB
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023 PDF 894.8 KB
MachXO5-NX-Hardware-Checklist
FPGA-TN-02274 1.7 7/15/2025 PDF 1.2 MB
MachXO5-NX High Speed IO Interface
FPGA-TN-02286 1.1 10/13/2025 PDF 3.7 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 2.5 10/13/2025 PDF 2.2 MB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.8 10/1/2025 PDF 2 MB
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-02081 1.1 8/27/2024 PDF 2.6 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.4 8/21/2024 PDF 3.5 MB
Triple-Speed Ethernet Driver API Reference
FPGA-TN-02341 1.2 6/26/2025 PDF 568.1 KB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.7 10/13/2025 PDF 1.9 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 2.8 10/13/2025 PDF 820.9 KB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
Adding Scalable Power and Thermal Management to Nexus FPGAs
FPGA-AN-02079 1.0 1/31/2024 PDF 1.3 MB
ADC User Guide for Nexus Platform
FPGA-TN-02129 2.1 10/13/2025 PDF 1.3 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.7 6/26/2024 PDF 1.3 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.6 12/10/2024 PDF 560.4 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 5.1 8/5/2025 PDF 693.7 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.6 12/10/2024 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 5.7 10/13/2025 PDF 1.1 MB
Using TraceID
FPGA-TN-02084 2.8 4/15/2025 PDF 493.8 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.5 3/6/2025 PDF 1.6 MB
MachXO5-NX-Family Root-of-Trust Devices Hardware Checklist
FPGA-TN-02371 1.0 6/26/2024 PDF 670.7 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Package Diagrams
FPGA-DS-02053 8.5 8/5/2025 PDF 9.4 MB
MachXO5-NX 25 Pinout
FPGA-SC-02038 1.0 5/26/2023 CSV 16.9 KB
MachXO5-NX 55T Pinout
FPGA-SC-02048 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 100T Pinout
FPGA-SC-02049 1.1 3/6/2024 CSV 16 KB
MachXO5-NX-20TD Pinout Table
FPGA-SC-02104 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX-20TDQ Pinout Table
FPGA-SC-02105 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX-55TDQ Pinout Table
FPGA-SC-02109 1.0 10/13/2025 CSV 15.9 KB
MachXO5-NX-30TDQ Pinout Table
FPGA-SC-02107 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX-30TD Pinout Table
FPGA-SC-02106 0.80 10/13/2025 CSV 19.2 KB
MachXO5-NX 55TD Pinout Table
FPGA-SC-02041 1.0 10/13/2025 CSV 16.3 KB
MachXO5-NX 15D-Pinout
FPGA-SC-02043 1.1 8/27/2025 CSV 16.1 KB
MachXO5-NX 65/T Pinout
FPGA-SC-02074 0.83 7/15/2025 CSV 21.4 KB
MachXO5-NX 35/T Pinout
FPGA-SC-02073 0.83 7/15/2025 CSV 21.4 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Advanced Key Management User Guide for MachXO5-NX
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instruction. 		2/21/2024 WEB
Embedded Security and Function Block User Guide for MachXO5-NX Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instruction. 		2/21/2024 WEB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.7 10/13/2025 PDF 1.9 MB
标题 编号 版本 日期 格式 文件大小
选择全部
Design Advisory for Nexus LVDS-based SGMII
FPGA-DA250601 1.0 6/3/2025 PDF 77.4 KB
标题 编号 版本 日期 格式 文件大小
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.8 10/13/2025 ZIP 3 MB
标题 编号 版本 日期 格式 文件大小
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Future-Proof Trust: Securing Digital Systems with Lattice RoT FPGAs and Complete CNSA 2.0 Algorithm Coverage
WP0047 1.0 10/13/2025 PDF 2.5 MB
在莱迪思FPGA中实现DC-SCM
WP0031 2.0 3/22/2023 PDF 1.2 MB
标题 编号 版本 日期 格式 文件大小
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[BSDL] LFMXO5-65T
FPGA-MD-02119 0.80 8/27/2025
[BSDL] LFMXO5-35T
FPGA-MD-02118 0.80 8/27/2025
[BSDL] LFMXO5-15D
FPGA-MD-02120 1.0 9/9/2025
[BSDL] LFMXO5-100
FPGA-MD-02043 1.14 4/18/2023 BSM 63.4 KB
[BSDL] LFMXO5-25
FPGA-MD-02027 1.14 5/31/2022 ZIP 18.9 KB
标题 编号 版本 日期 格式 文件大小
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MachXO5-NX Device Family Delphi Models
FPGA-MD-02031 1.5 10/13/2025 ZIP 45.7 KB
标题 编号 版本 日期 格式 文件大小
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MachXO5-NX IBIS Model file
FPGA-MD-02035 1.4 10/14/2025 ZIP 16.4 MB
[IBIS] MachXO5-NX
FPGA-MD-02035 1.3 7/15/2025 ZIP 16.1 MB

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