Lattice Solutions

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.

Platform Manager 2 & L-ASC10, MachXO3 

Mixed-Signal, Power Management, TOR Switch, Guidance Systems, 5G, Defense, SDR, Smart munitions 

IP Core

​​eSPI Target IP Core​

​​Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.​

MachXO5-NX, Mach-NX, MachXO3D, MachXO3, MachXO2 

APB, AHB-Lite, Lattice Sentry, OCP 

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

Certus-N2, MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR, Avionics 

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Certus-N2, Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X, iCE40 Ultra / UltraLite 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX, Certus-N2 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

​​The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.​

Certus-N2, Avant-G, Avant-X, Avant-E, MachXO5-NX, MachXO3D, MachXO3, Mach-NX 

MPESTI, UART, APB, Lattice Sentry, OCP 

Reference Design

MPESTI Initiator Reference Design

MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.

Avant-E, MachXO5-NX, MachXO3, MachXO3D 

MPESTI, UART, APB, AHB, RISC-V, OCP 

Reference Design

APB to AHB-Lite Bridge Reference Design

The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.

MachXO3D, MachXO3, MachXO2 

APB, AHB, AMBA 

IP Core

DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.

CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX 

CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 

Reference Design

JTAG Embedded Programming using RPi Reference Design

Demo connects Raspberry Pi GPIO pins to JTAG source code in Lattice Radiant™ and Diamond™ software for embedded development and hardware testing.

MachXO2, MachXO3, MachXO3D, CertusPro-NX, CrossLink-NX, MachXO5-NX, Mach-NX, Certus-NX 

JTAG, Raspberry Pi, GPIO 

Reference Design

LVDS Tunneling Protocol and Interface Reference Design

The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.

MachXO5-NX, MachXO3D, MachXO3, Mach-NX 

CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 

Reference Design

SSPI Embedded Programming using RPi Reference Design

SSPI Embedded Programming reference design provides several benefits, such as low power consumption and reasonable CPU, GPU, and memory performance.

CertusPro-NX, CrossLink-NX, CrossLinkPlus, CrossLink, MachXO3, MachXO2 

SSPI, Raspberry Pi 

Reference Design

I2C to APB Bridge Reference Design

With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.

MachXO2, MachXO3, MachXO3D 

I2C, APB, AMBA, AHB 

IP Core

SPI Sub IP Core

The SPI Sub IP Core is a versatile, efficient solution for SPI communication between an FPGA and a microcontroller, SoC, or another FPGA.

Avant-E, Avant-G, Avant-X, MachXO5-NX, CertusPro-NX, Certus-NX, MachXO3, ECP5 / ECP5-5G 

AXI, SPI 

IP Core

AHB-Lite Interconnect Module

A fully parameterized soft IP, high performance, low latency interconnect fabric for AMBA 3 AHB-Lite based systems, enabling one or more managers to be connected to one or more subordinates.

Certus-N2, Avant-G, Avant-X, Avant-E, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO2, MachXO3, MachXO3D, Mach-NX, MachXO5-NX 

AMBA, Lattice Propel, AHB-Lite, TOR Switch, Automotive 

IP Core

APB Interconnect IP Core

Propel IP Module: Fully parameterized to connect up to 32 APB bus masters and 32 slaves. Data bus width up to 32 bits. Address width up to 32 bits.

Certus-N2, CertusPro-NX, Avant-E, Avant-G, Avant-X, MachXO2, MachXO3, MachXO3D, Mach-NX, MachXO5-NX, CrossLink-NX, Certus-NX, iCE40 UltraPlus 

AMBA, APB, Lattice Propel, Automotive 

Reference Design

Generic Soft SPI Master Controller Reference Design

Provides an interface between a generic processor with parallel bus interface and external SPI devices.

MachXO2, MachXO3, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 

SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Demo

Soft I2C Master and Slave – Simple Write and Read

Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.

iCE40 UltraPlus, MachXO3 

Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C