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  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • Certus-N2 Evaluation Board

    Board

    Certus-N2 Evaluation Board

    Certus-N2 Evaluation Board is designed for evaluating and developing with the Certus-N2 family and supports 16G Serdes, LPDDR4, PCI-Gen4.
    Certus-N2 Evaluation Board
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • AXI4 to AHB-Lite Bridge Module

    IP Core

    AXI4 to AHB-Lite Bridge Module

    Lattice Semiconductor AXI4 to AHB-Lite Bridge Module provides an interface between the high-speed AXI4 and AHB-Lite.
    AXI4 to AHB-Lite Bridge Module
  • Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

    IP Core

    Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

    ​​The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.​
    Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
  • AXI4 Interconnect IP Core

    IP Core

    AXI4 Interconnect IP Core

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect IP Core
  • Video Scaler IP Core

    IP Core

    Video Scaler IP Core

    The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
    Video Scaler IP Core
  • I/O Interface IP Core

    IP Core

    I/O Interface IP Core

    Lattice Semiconductor’s IO Interface attribute acts as a memory interface to access valid addresses for GPO register writes and GPI register reads.
  • ​​Mutex IP Core​

    IP Core

    ​​Mutex IP Core​

    ​​Lattice Semiconductor’s Mutex IP provides several mutex registers for processors to claim exclusive access to one or more resources.​
  • Joint Test Action Group (JTAG) Bridge IP Core

    IP Core

    Joint Test Action Group (JTAG) Bridge IP Core

    The Lattice Semiconductor JTAG Bridge IP provides an efficient solution for debugging on-board issues by allowing you to access memory and peripheral registers directly using this IP, without involving the processor.
  • RISC-V AHB-L I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V AHB-L I/O Physical Memory Protection (IOPMP) IP Core

    Lattice Semiconductor’s RISC-V AHB-L IOPMP IP is a standalone memory protection unit that prevents illegal or unexpected access to specific memory regions.
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