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  • 10G Ethernet IP Core

    IP Core

    10G Ethernet IP Core

    The Lattice 10G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10G Ethernet IP Core
  • 25G Ethernet IP Core

    IP Core

    25G Ethernet IP Core

    The Lattice Semiconductor 25G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    25G Ethernet IP Core
  • Avant-E Evaluation Board

    Board

    Avant-E Evaluation Board

    The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
    Avant-E Evaluation Board
  • Avant-X Versa Board

    Board

    Avant-X Versa Board

    Avant-X Versa Board support devices that offers a modernized feature set for accelerated system design and fastest soft error detect (SED).
    Avant-X Versa Board
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • MACsec AES256-GCM, High-speed (XIP1213H)

    IP Core

    MACsec AES256-GCM, High-speed (XIP1213H)

    The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
    MACsec AES256-GCM, High-speed (XIP1213H)
  • ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    IP Core

    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • Lattice Sentry QSPI Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.
    Lattice Sentry QSPI Monitor IP Core for MachXO3D
  • Advanced CNN Accelerator IP

    IP Core

    Advanced CNN Accelerator IP

    Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.
    Advanced CNN Accelerator IP
  • Close Loop BLDC Motion Control Reference Design

    Reference Design

    Close Loop BLDC Motion Control Reference Design

    Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system
    Close Loop BLDC Motion Control Reference Design
  • CrossLinkU-NX UVC Streaming Reference Design

    Reference Design

    CrossLinkU-NX UVC Streaming Reference Design

    UVC streaming Reference Design provides a template for video streaming from camera sensor over the USB hard IP in the CrossLinkU-NX device to a USB host.
    CrossLinkU-NX UVC Streaming Reference Design
  • Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo

    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP
  • Lattice QSPI to NXP MPU Interface Reference Design

    Reference Design

    Lattice QSPI to NXP MPU Interface Reference Design

    This Lattice and NXP joint solution is designed to implement FlexSPI communication and expedite deployment using the Lattice ECP5 Evaluation Board.
    Lattice QSPI to NXP MPU Interface Reference Design
  • DisplayPort & Video Scaler Reference Design

    Reference Design

    DisplayPort & Video Scaler Reference Design

    The Lattice Drive DisplayPort & Video Scaler Reference Design implements easy evaluation of various DisplayPort interface.
    DisplayPort & Video Scaler Reference Design
  • MIPI CSI-2 to Ethernet Reference Design

    Reference Design

    MIPI CSI-2 to Ethernet Reference Design

    The MIPI CSI-2 to Ethernet reference design is an advanced system that integrates two camera sensors with each Lattice Avant™ Versa board.
    MIPI CSI-2 to Ethernet Reference Design
  • Lattice Sentry 4.0 Demo Board for MachXO5D-NX

    Board

    Lattice Sentry 4.0 Demo Board for MachXO5D-NX

    A complete platform to help you develop and test a NIST 800-193-compliant PFR solution and help in SoC project in Lattice Radiant and Propel 2024.1 Tools.
    Lattice Sentry 4.0 Demo Board for MachXO5D-NX
  • Lattice Sentry Demo Board for Mach-NX

    Board

    Lattice Sentry Demo Board for Mach-NX

    A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
    Lattice Sentry Demo Board for Mach-NX
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