Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support














Tags































Providers



Clear All
  • 25G Ethernet IP Core

    IP Core

    25G Ethernet IP Core

    The Lattice Semiconductor 25G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    25G Ethernet IP Core
  • 2.5G Ethernet MAC+PHY IP Core

    IP Core

    2.5G Ethernet MAC+PHY IP Core

    The Lattice 2.5G Ethernet MAC + PHY IP core implements the Media Access Controller (MAC) and state machine functions for the Physical Coding Sub-layer (PCS) described in the IEEE 802.3 (1000BASE-X) specification.
  • 10 Gb Ethernet MAC & PCS Reference Design

    Reference Design

    10 Gb Ethernet MAC & PCS Reference Design

    10Gb Ethernet MAC & PCS Reference Design on CertusPro-NX with data generator and checker.
    10 Gb Ethernet MAC & PCS Reference Design
  • MDIO Leader IP Core

    IP Core

    MDIO Leader IP Core

    MDIO LEADER IP features three different standard interfaces for accessing the control and status signals of Leader: APB, AHB-L and AXI-L.
    MDIO Leader IP Core
  • Time Sensitive Networking (TSN) End Node

    IP Core

    Time Sensitive Networking (TSN) End Node

    The Time Sensitive Networking (TSN) End Node IP supports scheduling, priority queues, credit shaping, cyclic forwarding and preemption.
    Time Sensitive Networking (TSN) End Node
  • Time Sensitive Networking (TSN) Network Node

    IP Core

    Time Sensitive Networking (TSN) Network Node

    Time Sensitive Networking (TSN) Switched End Node IP supports 3 Ports, scheduling, priority queues, credit shaping, redundancy, cyclic forwarding and preemption
    Time Sensitive Networking (TSN) Network Node
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • MDIO Peripheral - WISHBONE Compatible

    Reference Design

    MDIO Peripheral - WISHBONE Compatible

    Implements an MDIO (Management Data Input/Output Interface) slave interface as specified in the IEEE 802.3 standard.
    MDIO Peripheral - WISHBONE Compatible
  • ​​Robo/TSN for Industrial Networks with Multi-Gig Ethernet​

    Reference Design

    ​​Robo/TSN for Industrial Networks with Multi-Gig Ethernet​

    MLE Robo/TSN virtualizes multi-Gigabit TSN and protocols, linking factory floor to cloud with SmartNICs scalable to 100 Gbps and beyond.​
    ​​Robo/TSN for Industrial Networks with Multi-Gig Ethernet​
  • ​​10G TCP/IP Stack for Network Acceleration​

    IP Core

    ​​10G TCP/IP Stack for Network Acceleration​

    ​​TCP/IP Full Accelerator for 10G connections, including TCP, IP, MAC layers. 128-bit full-duplex, pipelined all-RTL design for ultra-low latency.
    ​​10G TCP/IP Stack for Network Acceleration​
  • ​​​​25G TCP/IP Stack for Network Acceleration​​

    IP Core

    ​​​​25G TCP/IP Stack for Network Acceleration​​

    ​​TCP/IP Full Accelerator for 25G connections, including TCP, IP, MAC layers. 128-bit full-duplex, pipelined all-RTL design for ultra-low latency.
    ​​​​25G TCP/IP Stack for Network Acceleration​​
  • ​​​25G UDP/IP Stack for Network Acceleration

    IP Core

    ​​​25G UDP/IP Stack for Network Acceleration

    ​​UDP/IP Full Accelerator for 25G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra-low latency.
    ​​​25G UDP/IP Stack for Network Acceleration
  • ​​10G UDP/IP Stack for Network Acceleration​

    IP Core

    ​​10G UDP/IP Stack for Network Acceleration​

    UDP/IP Full Accelerator for 10G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra-low latency.​
    ​​10G UDP/IP Stack for Network Acceleration​
  • Page 1 of 1
    First Previous
    1
    Next Last