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  • ​​eSPI Target IP Core​

    IP Core

    ​​eSPI Target IP Core​

    ​​Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.​
    ​​eSPI Target IP Core​
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • Lattice Sentry PLD Interface IP Core

    IP Core

    Lattice Sentry PLD Interface IP Core

    Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
    Lattice Sentry PLD Interface IP Core
  • Lattice Sentry ESB Mux IP Core for MachXO3D

    IP Core

    Lattice Sentry ESB Mux IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Enables access the MachXO3D embedded security block (ESB) simultaneously with internal crytographic operations
    Lattice Sentry ESB Mux IP Core for MachXO3D
  • Lattice Sentry I2C Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry I2C Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on I2C bus to identify and block potentially illegal traffic.
    Lattice Sentry I2C Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.
    Lattice Sentry QSPI Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Streamer IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Streamer IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Provides fast SPI memory access for firmware authentication as part fo Platform Root of Trust operation
    Lattice Sentry QSPI Streamer IP Core for MachXO3D
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

    IP Core

    Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

    ​​The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.​
    Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    MPESTI Initiator Reference Design
  • APB to AHB-Lite Bridge Reference Design

    Reference Design

    APB to AHB-Lite Bridge Reference Design

    The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.
    APB to AHB-Lite Bridge Reference Design
  • DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    I2C to APB Bridge Reference Design
  • 2.5G Ethernet MAC+PHY IP Core

    IP Core

    2.5G Ethernet MAC+PHY IP Core

    The Lattice 2.5G Ethernet MAC + PHY IP core implements the Media Access Controller (MAC) and state machine functions for the Physical Coding Sub-layer (PCS) described in the IEEE 802.3 (1000BASE-X) specification.
  • MDIO Leader IP Core

    IP Core

    MDIO Leader IP Core

    MDIO LEADER IP features three different standard interfaces for accessing the control and status signals of Leader: APB, AHB-L and AXI-L.
    MDIO Leader IP Core
  • Memory Controller IP Core

    IP Core

    Memory Controller IP Core

    The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design.
    Memory Controller IP Core
  • SLVS-EC Receiver IP Core

    IP Core

    SLVS-EC Receiver IP Core

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    SLVS-EC Receiver IP Core
  • SPI Flash Memory Controller IP Core

    IP Core

    SPI Flash Memory Controller IP Core

    The SPI Flash Memory Controller IP Core provides an industry-standard interface between a CPU and an off-chip SPI flash memory device.
    SPI Flash Memory Controller IP Core
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