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  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX, MachXO3D, MachXO2, iCE40 UltraPlus 
    Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense, AHB-Lite 
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 
    Embedded Ram, FIFO, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, Certus-NX, CertusPro-NX, Lattice Propel System Design Environment 
    Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 
    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.
    Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX, Certus-N2 
    AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 
    Timer/Counter IP Core
  • DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX 
    CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 
    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core
  • MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design

    Reference Design

    MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design

    The Lattice Semiconductor MachXO5™-NX LFMXO5-55TD (also referred to as MachXO5-NX-55TD or MachXO5-55TD) soft boundary-scan (BSCAN) reference design enables boundary scan testing through a soft JTAG interface to enhance device security, external access to the hardware JTAG port is disabled. Therefore, board-level boundary scan testing must be performed using the soft JTAG boundary-scan IP core.
     
    Lattice Radiant 
    MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design
  • 2.5G Ethernet MAC+PHY IP Core

    IP Core

    2.5G Ethernet MAC+PHY IP Core

    The Lattice 2.5G Ethernet MAC + PHY IP core implements the Media Access Controller (MAC) and state machine functions for the Physical Coding Sub-layer (PCS) described in the IEEE 802.3 (1000BASE-X) specification.
    MachXO5-NX, CertusPro-NX 
    Lattice Radiant, APB, Ethernet, PCS, IEEE 802.3, Ethernet Bundle 
  • AXI Register Slice IP Core

    IP Core

    AXI Register Slice IP Core

    The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.
    LatticeECP3, ECP5 / ECP5-5G, CrossLink-NX, Certus-NX, MachXO5-NX, CertusPro-NX, Avant-E, Certus-N2 
    AXI, AXI-Lite Interface, Lattice Propel, Lattice Radiant 
    AXI Register Slice IP Core
  • Flash Access IP Core

    IP Core

    Flash Access IP Core

    The Flash Access for MachXO5-NX IP Core enables you to perform write and read access to the internal flash memory of LFMXO5-25 device.
    MachXO5-NX 
    Bus Controllers, Security, Automotive, Flash, Timer, Memory Controller, Lattice Radiant 
    Flash Access IP Core
  • Avant MPPHY Module

    Avant MPPHY Module

    The MPPHY Module supports the most common high-speed SERDES protocols used for inter-chip connectivity.
    Avant-G, Avant-X 
    Lattice Avant, Lattice Radiant, PCS, PMA, SERDES 
    Avant MPPHY Module
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