M-PESTI is a generic and extensible 1-wire, bidirectional circuit and protocol for applications such as cabled high-speed I/O interposers, managed power distribution, cooling systems, and other sensors. This reference design aims to provide M-PESTI as an SoC peripheral with a RISC-V core.
This version of the M-PESTI Initiator Reference Design provides a Lattice Propel solution template that uses the M-PESTI Initiator IP core with a reference driver/firmware, RISC-V core with other required IP modules, and M-PESTI Target test component. The reference design is compliant with the M-PESTI Base Specification (part of the DC-MIS version 1.0 specification). The Reference Design includes the following collaterals:
- The SoC design project on which you can view, open, and modify the design through the Lattice Propel™ Builder software. The bitstream can be generated using the Lattice Diamond™ software.
- The SoC workspace, which includes necessary drivers for configuring both peripheral IPs and firmware for the demonstration.
- The CPLD demonstration bitstream
To learn more about this product design and if you need the old source code, please Submit a Technical Support Case Ticket