RISC-V MC CPU IP Core

RISC-V for Micro-Controller Applications

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The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

Resource Utilization details are available in the IP Core User Guide.

Features

  • RV32IMCE instruction set
  • Five stages of pipelines
  • Supports the AHB-Lite bus standard for instruction and data ports.
  • Supports CXU-LI
  • Supports RVFI

Block Diagram

Ordering Information

The RISC-V MC CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V MC CPU IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02300 1.0 12/11/2025 PDF 956.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Small-sized RISC-V CPU IP Core- Lattice Propel Builder
FPGA-IPUG-02114 1.0 6/3/2020 PDF 1.4 MB
RISC-V MC CPU IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02300 1.0 12/11/2025 PDF 956.7 KB

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