RISC-V MC CPU IP Core

RISC-V for Micro-Controller Applications

The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

Resource Utilization details are available in the IP Core User Guide.

Features

  • RV32IMC instruction set
  • Five stages of pipelines
  • Support the AHB-L bus standard for instruction/data port
  • Optional caches, including a 4 KB two-way instruction cache and a 4 KB two-way data cache (for Lattice Avant, MachXO5-NX, Certus-NX, CertusPro-NX, and CrossLink-NX only)
  • Optional debug using Gnu Debugger (GDB) and Open On-Chip Debugger (OpenOCD)

Block Diagram

Ordering Information

The RISC-V MC CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Small-sized RISC-V CPU IP Core- Lattice Propel Builder
FPGA-IPUG-02114 1.0 6/3/2020 PDF 1.4 MB
RISC-V MC CPU (Micro-Controller) IP Module User Guide - Lattice Propel Builder
FPGA-IPUG-02278 1.1 7/30/2025 PDF 1 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.