RISC-V RX CPU IP Core

RISC-V for RTOS Applications

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The Lattice Semiconductor RISC-V RX soft IP contains a 32-bit RISC-V processor core and several submodules – Platform Level Interrupt Controller (PLIC), Core Local Interrupter (CLINT), and Watchdog. The CPU core supports the RV32IMACF instruction set and the debug feature which is JTAG – IEEE 1149.1 compliant.

Resource Utilization details are available in the IP Core User Guide.

Features

  • RV32IMACF instruction set
  • Five-stage pipeline
  • Three privilege modes supported: Machine mode, Supervisor mode, and User mode
  • Four processor modes supported: Advanced mode, Balanced mode, Lite mode, and Fmax mode
  • Instruction Cache and Data Cache

Block Diagram

RISC-V RX CPU IP Core_BDExpand Image

Ordering Information

The RISC-V RX CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V RX CPU IP Core – Lattice Propel Builder 2025.1.1 User Guide
FPGA-IPUG-02298 1.0 10/10/2025 PDF 1.6 MB

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