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  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    Reference Design

    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core
  • Octal SPI Controller IP Core

    IP Core

    Octal SPI Controller IP Core

    ​​Octal SPI Controller IP Core supports various types of SPI protocols & provides a flexible Transaction Layer Interface to the PCI Express Bus.​
    Octal SPI Controller IP Core
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • AXI4 to AHB-Lite Bridge Module

    IP Core

    AXI4 to AHB-Lite Bridge Module

    Lattice Semiconductor AXI4 to AHB-Lite Bridge Module provides an interface between the high-speed AXI4 and AHB-Lite.
    AXI4 to AHB-Lite Bridge Module
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
  • AXI4 Interconnect IP Core

    IP Core

    AXI4 Interconnect IP Core

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect IP Core
  • CrossLinkU-NX UVC Streaming Reference Design

    Reference Design

    CrossLinkU-NX UVC Streaming Reference Design

    UVC streaming Reference Design provides a template for video streaming from camera sensor over the USB hard IP in the CrossLinkU-NX device to a USB host.
    CrossLinkU-NX UVC Streaming Reference Design
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