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  • Unified Interconnect IP Core

    IP Core

    Unified Interconnect IP Core

    A high-performance and low-latency interconnect fabric for AXI4- and AXI4-Lite-based systems.
    Unified Interconnect IP Core
  • FFT 编译器

    IP Core

    FFT 编译器

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT 编译器
  • FIR 滤波器生成器

    IP Core

    FIR 滤波器生成器

    可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
    FIR 滤波器生成器
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • CrossLinkU-NX评估板

    Board

    CrossLinkU-NX评估板

    CrossLinkU-NX评估板是一个使用CrossLinkU-NX器件进行通用应用开发的平台,CrossLinkU-NX器件是首款具有硬核USB2/3(5Gbps)接口的FPGA。
    CrossLinkU-NX评估板
  • USB 2.0/3.2 IP核

    IP Core

    USB 2.0/3.2 IP核

    莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案,适用于莱迪思CrossLink-NX FPGA最新器件。
    USB 2.0/3.2 IP核
  • USB到I/O聚合和桥接参考设计

    Reference Design

    USB到I/O聚合和桥接参考设计

    USB到I/O桥接参考设计为支持USB的FPGA提供即插即用外设扩展,还支持从USB到I2C、SPI和GPIO的信号协议转换。
    USB到I/O聚合和桥接参考设计
  • Crosslink-NX PCIe桥接板上的PCIe基础演示

    演示

    Crosslink-NX PCIe桥接板上的PCIe基础演示

    该PCIe基础演示可以控制三个7段LED,并通过PCIe插槽操作FPGA的片上存储器。
    Crosslink-NX PCIe桥接板上的PCIe基础演示
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    演示

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    演示

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • 基于莱迪思Nexus FPGA的PCIe多功能演示

    演示

  • CrossLink-NX-33 Voice and Vision Machine Learning Board

    Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board is designed using Crosslink-NX 33K, ideal for machine learning applications.
    CrossLink-NX-33 Voice and Vision Machine Learning Board
  • CrossLink-NX声音和视觉机器学习板

    Board

    CrossLink-NX声音和视觉机器学习板

    专为采用莱迪思sensAI和CrossLink-NX器件的低功耗机器学习应用而设计。包括图像传感器、麦克风、HyperRAM和扩展端口。
    CrossLink-NX声音和视觉机器学习板
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • RISC-V RX CPU IP核

    IP Core

    RISC-V RX CPU IP核

    莱迪思RISC-V RX IP使用32位RISC-V处理器核和多个子模块,在监控外部中断的同时处理数据和指令。
    RISC-V RX CPU IP核
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
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