Lattice Solutions

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Certus-N2, Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3 – 制御/ブリッジFPGA, MachXO2, Avant-G, Avant-X, iCE40 Ultra / UltraLite 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V Nano CPU IP Core

The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.

Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX, MachXO3D, MachXO2, iCE40 UltraPlus, MachXO4 

Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense, AHB-Lite 

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3 – 制御/ブリッジFPGA, MachXO3D, MachXO5-NX, Certus-N2 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

Demo

Single Wire Signal Aggregation Demonstration

Single Wire Signal Aggregation Demonstration contains two boards to demonstrate the complete working design in a stand-alone configuration.

iCE40 UltraPlus 

Single Wire, Signal Aggregation, Bus Controllers, GPIO, I2C, I2S, UART, Defense 

Reference Design

シングルワイヤ・アグリゲーション

FPGAを利用したシングルワイヤ・アグリゲーションと伝送で、PCBの混雑を緩和

iCE40 UltraPlus 

Bus Controllers, Signal Aggregation, Single Wire, Defense 

Reference Design

人感検出

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.

iCE40 UltraPlus 

Machine Learning/AI, Object Detection, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense 

IP Core

I3C スレーブ IP コア

CrossLink-NX 用ラティス I3C インタフェースは、バスが使用する電力を大幅に効率化しながら、I2C よりも 10 倍以上の速度向上を実現します。

CertusPro-NX, CrossLink-NX, Certus-NX, MachXO5-NX, iCE40 UltraPlus, Avant-E, Avant-G, Avant-X, Certus-N2, MachXO3D, Mach-NX 

I3C, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, 5G, Automotive, MIPI Bundle 

IP Core

I3C マスタ IP コア

CrossLink-NX 用 I3C インタフェースは、バスが使用する電力を大幅に効率化しながら、I2C よりも 10 倍以上の速度向上を実現します。

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, iCE40 UltraPlus, Avant-E, Avant-G, Avant-X, Certus-N2, MachXO3D, Mach-NX 

I3C, Bus Controllers, TOR Switch, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Defense, 5G, Automotive, MIPI Bundle, Lattice Sentry 

IP Core

USB 2.0 Device with FIFO Interface (USB20HF)

USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.

CrossLink-NX, iCE40 UltraPlus, MachXO2 

FMC, Data Communication, Camera, ULPI, USB2, FIFO 

Board

iCE40 UltraPlusブレークアウトボード

General purpose board for evaluation and development with iCE40 UltraPlus. Includes access to all IO, high-current LED, switches, etc.

iCE40 UltraPlus 

Breakout, LED Control, Defense, Avionics 

Board

Single Wire Signal Aggregation Development Board

Single Wire Signal Aggregation Dev Board uses the smallest form factor FPGAs to perform as a Single-Wire aggregator for I2C, I2S, UART, & GPIO signaling.

iCE40 UltraPlus 

Single Wire, Signal Aggregation, Bus Controllers, GPIO, I2C, I2S, UART, Defense, Avionics 

Board

iCEstick 評価キット

低コスト、USBフォームファクタのiCE40評価ボード

iCE40 

Breakout, IrDA, PMOD, UART 

Board

iCE40 Ultraブレークアウトボード

A simple, low-cost board with rich IO access for evaluation and development with the iCE40 Ultra FPGA.

iCE40 Ultra / UltraLite 

Breakout, LED Control 

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU

iCE40 UltraPlus, MachXO2 

UART, Bus Controllers, TOR Switch 

IP Core

APB Interconnect IP Module

Propel IP Module: Fully parameterized to connect up to 32 APB bus masters and 32 slaves. Data bus width up to 32 bits. Address width up to 32 bits.

Certus-N2, CertusPro-NX, Avant-E, Avant-G, Avant-X, MachXO2, MachXO3 – 制御/ブリッジFPGA, MachXO3D, Mach-NX, MachXO5-NX, CrossLink-NX, Certus-NX, iCE40 UltraPlus, MachXO4 

AMBA, APB, Lattice Propel, Automotive 

Reference Design

Generic Soft SPI Master Controller Reference Design

Provides an interface between a generic processor with parallel bus interface and external SPI devices.

MachXO2, MachXO3 – 制御/ブリッジFPGA, LatticeECP3, ECP5 / ECP5-5G, CrossLink, CrossLink-NX, iCE40 UltraPlus 

SPI, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 – 制御/ブリッジFPGA, Mach-NX 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

Demo

Soft I2C Master and Slave – Simple Write and Read

Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.

iCE40 UltraPlus, MachXO3 – 制御/ブリッジFPGA 

Computing, IoT, TOR Switch, Bus Controllers, I2C 

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

CrossLink, CrossLink-NX, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 UltraPlus, LatticeECP3, MachXO2, MachXO3 – 制御/ブリッジFPGA 

5G, Computing, IoT, TOR Switch, Bus Controllers, I2C 

IP Core

GPIO IP コア

汎用入出力 (GPIO) ペリフェラル・ソフト IP は、CrossLink-NX用のラティス メモリ・マップド・インタフェース (LMMI) または アドバンスド・ペリフェラル・バス・インタフェース (APB) を経由して GPIO を制御します。

CertusPro-NX, Certus-NX, CrossLink-NX, Mach-NX, iCE40 UltraPlus, MachXO5-NX, Avant-E, Avant-G, Avant-X, Certus-N2 

GPIO Control, APB, Bus Controllers, TOR Switch, Automotive