The Lattice I3C Target IP core supports several communication formats, all sharing a two-wire interface: SDA bidirectional data line and SCL bidirectional clock. It monitors the I3C bus for relevant I3C commands sent by the I3C Controller and responds accordingly. Also, this IP accepts commands from LMMI or from the optional APB/AHB-Lite interface.
The Lattice I3C IP is designed to comply with the MIPI I3C specification. The MIPI I3C interface eases sensor system design architectures in mobile wireless products by providing a fast, low-cost, low-power, two-wire digital interface for sensors. I3C protocol is a single scalable, cost effective, and a power efficient protocol. Implementing the I3C specification greatly increases the implementation flexibility for an ever-expanding sensor subsystem as efficiently and at as low cost as possible.
Resource Utilization details are available in the IP Core User Guide.