GHRD/GSRD Demonstration

A Collection of Hardware and Software for Developing Various Applications

The Golden System Reference Design (GSRD) and the Golden Hardware Reference Design (GHRD) comprise a collection of software and hardware components for developing various applications using the Lattice FPGA.

The GSRD is a collection of software and hardware components for developing a wide variety of end-user applications using the Lattice FPGA. The GSRD architecture provides a base level FPGA system design that allows users to add or remove any additional soft-IPs or custom IPs, without having to build the entire FPGA system from scratch. You can focus on integration and testing your own developed blocks and scale your application accordingly. The GSRD demo also showcase various complex soft-IP features, systems, and tool capabilities to help you understand Lattice FPGA devices better.

Features

  • Support RISC-V RX/MC Soft CPU, AXI4 Interconnect and AHB-Lite Interconnect
  • Octal SPI Controller, QSPI Flash Controller and on-chip System Memory
  • APB connected UART, GPIO and LED output
  • Memory Controller with LPDDR4 support
  • RGMII/SGMII Gigabit Ethernet interface and SGDMA data transfer IP

Jump to

Block Diagram

GHRD/GSRD Reference Design and Demo version 1.0 block diagram for Avant-E

GHRD/GSRD Reference Design and Demo version 2.0 block diagram for CertusPro-NX​

GHRD/GSRD Reference Design and Demo version 2.0 block diagram for Avant-E​

GHRD/GSRD Reference Design and Demo version 3.0 block diagram for CertusPro-NX​

GHRD/GSRD Reference Design and Demo version 1.0 block diagram for Certus-NX​

Release Version

GHRD/GSRD Name GHRD/GSRD Version Supported FPGA Family Supported FPGA Board Name Lattice Radiant Software Version Lattice Propel Design Environment Version U-boot Branch (Tag)
Golden System Reference Design for CertusPro-NX 3.0 CertusPro-NX CertusPro-NX Versa Board 2025.1.1 2025.1.1 -
Golden System Reference Design for CertusPro-NX 2.0 CertusPro-NX CertusPro-NX Versa Board 2024.1.1 2024.1 Branch = lattice_v2024.04
Tag = lattice_gsrd_2024_01
Golden System Reference Design for Avant-E 2.0 Avant-E Avant-E Evaluation Board 2025.1.1 2025.1.1 -
Golden System Reference Design for Avant-E 1.0 Avant-E Avant-E Evaluation Board 2024.1.1 2024.1 -
Golden System Reference Design for Certus-NX 1.0 Certus-NX Certus-NX Versa Evaluation Board 2025.1.1 2025.1.1 -

* The flash device on CertusPro-NX Versa Board is a Winbond W25Q512JVEIQ or Macronix MX25L51245G.
* The CertusPro-NX Golden System Reference Design and Demo V2.0 – Bitstream can be programmed to Winbond W25Q512JVEIQ flash only.
* Refer to FAQ#7540 for guidance to update the Golden System Reference Design for CertusPro-NX version 2.0 bitstream based on the flash manufacturer on your CertusPro-NX Versa Board.

Documentation

技术资源
下载
标题 编号 版本 日期 格式 文件大小
选择全部
Avant-E Golden System Reference Design and Demo V1.0 - User Guide
FPGA-RD-02296 1.0 2/24/2025 PDF 4.9 MB
CertusPro-NX Golden System Reference Design and Demo V2.0 - User Guide​
FPGA-RD-02300 1.0 10/28/2024 PDF 6.7 MB
CertusPro-NX Golden System Reference Design and Demo V3.0 - User Guide
FPGA-RD-02322 1.0 10/31/2025 PDF 6.3 MB
Certus-NX Golden System Reference Design and Demo V1.0 - User Guide
FPGA-RD-02323 1.0 10/31/2025 PDF 6.1 MB
Avant-E Golden System Reference Design and Demo V2.0 - User Guide
FPGA-RD-02324 1.0 10/31/2025 PDF 6.7 MB
标题 编号 版本 日期 格式 文件大小
选择全部
CertusPro-NX Golden System Reference Design and Demo V3.0 - Bitstream
10/31/2025 ZIP 10.4 MB
Certus-NX Golden System Reference Design and Demo V1.0 - Bitstream
10/31/2025 ZIP 2.5 MB
Avant-E Golden System Reference Design and Demo V2.0 - Bitstream
10/31/2025 ZIP 11.1 MB
Avant-E Golden System Reference Design and Demo V1.0 - Bitstream
2/24/2025 ZIP 21.5 MB
CertusPro-NX Golden System Reference Design and Demo V2.0 - Bitstream
10/28/2024 ZIP 7.2 MB