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    ID
    Family
    Category
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  • All FPGA: What is the initial logic level of a register after power-up?
    204
    All FPGA
    Architecture
    General Logic
  • What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
    203
    All FPGA
    Customer Board Design
    Layout Review
  • What are the pin location requirements when using an input clock to capture input data?
    202
    All FPGA
    Customer Board Design
    Layout Review
  • How to solve the issue of "ispVM System  doesn't detect  parallel port ISP Download Cable" ?
    209
    All FPGA
    Device Programming
    ispVM System
  • LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?
    2095
    All FPGA
    Architecture
    Memory EBR/Distributed
  • Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?
    200
    All FPGA
    Implementation
    Timing Analysis
  • Power Manager 2: Does it allow to read a 1.0 Volt signal from the ADC with attenuator setting 1…
    2093
    Power Manager II
    Architecture
    I2C
  • LatticeECP3: Is it allowable to bypass the PCS 8B10B encoding/decoding function and still use the…
    2099
    All FPGA
    Architecture
    SERDES/PCS
  • LatticeECP3/SGMII: Does the different number of preambles (5 or 6) on the Lattice SGMII IP (Serial…
    2097
    LatticeECP3
    Lattice IP/Reference Design
    SGMII
  • Power Manger II: Can the POWR1220AT8 be used to monitor negative voltages?
    2040
    Power Manager II
    Architecture
    IO
  • XP2: Does ispVM Embedded support TAG memory operations with the XP2?
    2049
    LatticeXP2
    Device Programming
    ispVM Embedded
  • LatticeXP2: Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?
    2043
    LatticeXP2
    Architecture
    Configuration/Programming
  • LatticeECP3: How to place DDR3 interface pins to minimize the SSO impact?
    2041
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • LatticeECP3: Should I run gate level simulations for the Peripheral Component Interconnect Express…
    2076
    LatticeECP3
    Lattice IP/Reference Design
    PCIe
  • LatticeECP3: Can the default BSDL file provided on the Lattice website be used to test a programmed…
    2077
    LatticeECP3
    Architecture
    JTAG
  • [ispMACH 4000]: I have 75 5V inputs to an ispMACH 4000 device. Which I/O type should I use between…
    2045
    ispMACH 4000
    Architecture
    IO
  • What is the optimum PCB solder mask opening and pad diameter for a Lattice package?
    2072
    All Devices
    Customer Board Design
    Layout
  • Diamond: Is there a limitation to the name that user can give for their project directory?
    2073
    All Devices
    Implementation
    Project Navigator
  • Power Manager II: What is the POR state of I2C controlled input and output pins in POWR1014A?
    2070
    Power Manager II
    Architecture
    IO
  • LatticeECP3 datasheet shows that LVDS (Low Voltage Differential Signal) output buffer can run at…
    2018
    LatticeECP3
    Architecture
    Generic DDR
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