The LatticeECP2M SMPTE SDI Evaluation Board utilizes high-speed SERDES interfaces to demonstrate SMPTE 259 and 292 capabilities. This board, along with associated peripheral cables, demonstration programs and IP cores, is a complete solution designed to demonstrate the integration of HD-SDI, SDI and DVB-ASI encoders and decoders into an FPGA. The board can also be used to aid in the development of custom designs for the LatticeECP2M FPGA.
Device Support
You will need the following software to use this board:
- ispLEVER for design, fitting, place & route of Lattice programmable devices
- ispVM to download your program to the LatticeECP2M or on-board Flash memory devices
- ORCAstra for on-chip FPGA register configuration.
LatticeECP2M SMPTE IP Solutions
The Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core is a complete SDI PHY interface that connects to the high-speed SDI serial data on one side and formatted parallel data on the other side. It supports SMPTE standards 125M, 259M, 260M, 267M, 274M, 292M, 295M, and 296M and comprises high-speed serial I/Os (serializer/de-serializer or SerDes), SDI encoder, decoder, word alignment logic, CRC detection and checking logic, and rate detection logic. It is optimized to work with the LatticeECP2M/S embedded Physical Coding Sublayer (PCS) and SerDes, enabling a complete, single-chip solution ideally suited for a wide set of applications requiring high-performance, high-integration, and low-cost.