Lattice Radiant Version History

Radiant Update 2025.1.1

  • Device Support
    • Certus™-NX (LFD2NX)
      • The BBG400 package for LFMXO5-35/65 and LFD2NX-35/65, as well as the CABGA256 package for LFD2NX-25, have been changed from 'generally available' to 'controlled access.'
      • To request for a license, you may raise a ticket to the Submit Support Ticket page.
    • Lattice Avant™-NX (LAV-AT)
      • E50 (-1/-2/-3) 0.82V (COM/IND) – CSG841
    • MachXO5™-NX (LFMXO5)
      • 35T (-7/-8/-9) 1.00V (COM/IND) – BBG256
      • 65T (-7/-8/-9) 1.00V (COM/IND) – BBG256
  • Tool and Other Enhancements
    • Device
      • The license string for -7 speed grade has been removed for LIFCL-17 UWG72 package.
        Note: This is now supported with Radiant free license.
      • The status of the following LAV-AT-E70 packages has been changed from “Advanced” to Preliminary”:
        • LFG676
        • CSG841
        • CBG484
    • Design Tcl Commands – Design commands now support the des_get_ram_cells and des_get_ram_style.
      • des_get_ram_cells retrieves memory cells that are implemented as either distributed RAM or block RAM.
      • des_get_ram_style returns the memory style of a specified RAM cell.
    • Programmer – Status check code after reboot has been removed. This avoids failure when the device exits user mode while STAPL is still trying to read the status register.

Radiant 2025.1

  • Device Support:
    • Certus™-N2 (LN2-CT-20ES)
      • 22 (-1/-2/-3) 0.82V (COM/IND) – ASG410
    • Certus™-NX (LFD2NX)
      • 9 (-7/-8/-9) 1.00V (COM/IND) – CSFBGA121, CABGA196
      • 15 (-7/-8/-9) 1.00V (COM/IND) – CABGA256, CABGA400
      • 17 (-7/-8/-9) 1.00V (COM/IND/AUTO) – CSFBGA121, CABGA196
      • 25 (-7/-8/-9) 1.00V (COM/IND) – CABGA256, CABGA400
      • 35 (-7/-8/-9) 1.00V (COM/IND) – CABGA400, CABGA484
      • 65 (-7/-8/-9) 1.00V (COM/IND) – CABGA400, CABGA484
    • MachXO5™-NX (LFMXO5)
      • 35 (-7/-8/-9) 1.00V (COM/IND) – BBG400
      • 35T (-7/-8/-9) 1.00V (COM/IND) – BBG484
      • 65 (-7/-8/-9) 1.00V (COM/IND) – BBG400
      • 65T (-7/-8/-9) 1.00V (COM/IND) – BBG484
  • Tool and Other Enhancements:
    • Command Line – The “sspi_cmd” command has been added to run SSPI commands for Nexus and Avant devices.
    • Lattice Synthesis Engine (LSE) – LSE now supports inference of byte write enable True Dual-Port RAM
    • License – The license support has been updated for various MachXO5-NX devices. Refer to the Supported Devices table on page 3 for more information.
    • Low Power Support – Dynamic Clock Control (DCC) has been added to support low power reduction in the LSE tool and MAP. This functionality is currently available as a Beta feature in this release.
    • Power Calculator –– The “(DPM)” text has been added in the Power Summary tab to support the table title Dynamic Power Multiplier.
    • Physical Designer – The "Resource Usage Count" and "Selected Resource Usage Count" sections are now in the Create GROUP dialog box of Physical Designer, showing the total resource count for all instances.
    • Place and Route (PAR)
      • The Physical Synthesis option has been integrated into Place and Route flow. This functionality is currently available as a Beta feature in this release.
      • The QoR improvement option “nexus_extreme” has been added to the PAR command line for Nexus devices. When enabled, the placement engine switches from Simulated Annealing (SA) to Analytical Placer (AP). AP can run faster with better timing results. This option is currently available as a Beta feature in this release.
    • Reports
      • The "Parameter Settings" section has been added to Synthesis Reports, displaying parameters for each instance when the design includes entities with parameters. This feature is available only for LSE.
      • The “Stage Execution Time Summary” section has been added to Project Summary.
      • The resource usage percentage has been added to Report Summary
    • Reveal
      • Support for incremental flow has been added to the post-par Reveal stage.
      • The interface for setting up virtual switch/LED signals has been enhanced for ordering and color coding.
      • A captured waveform can now be saved as an RVA file and reloaded when Reveal Analyzer is reopened.
      • Support for memory controller debug for Avant devices has been added to diagnose and resolve DDR interface issues
    • Strategies
      • The “Set VIRTUAL IO on all ports” strategy has been added to strategy settings. This option adds virtual IO information to MAP reports when enabled.
      • The “Use DCC Insertion” option has been added to LSE options to support low power reduction.
    • TCL Console
      • The Radiant TCL console (radiantc) now supports argument handling.

Radiant Update 2024.2.1

  • Device Support:
    • Lattice Avant™ (LAV-AT)
      • E50 (-1/-2/-3) 0.82V (COM/IND) – CBG484
      • E70 (-1/-2/-3) 0.82V (COM/IND) – CBG484, LFG676, CSG841, LFG1156
  • Tool and Other Enhancements:
    • Device – Security bitstream and GUI, Programming, and Reveal Debugger have been updated to support the LAV-AT-E50 and LAV-AT-E70 devices.
    • Reveal
      • Reveal debugger (Logic Analyzer and Controller) supports latest Avant-E70 and Avant-E50 silicon.
      • For Avant devices, Reveal supports SerDes debugging with IBERT (Integrated Bit Error Tester) and the optimization of transceiver channels.

Radiant 2024.2

  • Device Support:
    • Certus™-N2 (LN2-CT-ES)
      • 22K (-1/-2/-3) 0.82V (COM/IND) – ASG410, CBG484
  • Tool and Other Enhancements:
    • Design Rule Checking – Lattice Synthesis Engine (LSE) now supports a standalone design rule checking flow to lint user RTL.
    • Power Calculator
      • The User Entered Tj has been added to Power Calculator Environment section allowing users to enter junction temperature directly.
      • Utilization table for each tab has been added to show the percentage of resources used for each IP after power calculations.
      • For devices that supports boundary scanning, a radio option has been added at the top of the I/O tab allowing users to enable or disable boundary scanning.
    • General Options – The Check Controlled Device License is enabled by default if Radiant is newly installed. You have to manually enable it if you are using previous Radiant versions.
    • Reports – The Radiant Report Summary now includes the IP Summary Report, which displays the Lattice IP utilized in the design.
    • Timing Analyzer – The Waveform tab provides a visual reference to the Data Path, demonstrating how and where the constraints have been applied.
    • Reveal – Reveal now supports beta version of post-PAR Reveal debugger.

Radiant Update 2024.1.1

  • Device Support:
    • Lattice Avant™ (LAV-AT)
      • E70ES1 (-1/-2/-3) 0.82V (COM/IND) – CSG841
      • Designs targeting the E70 device in 2023.2 or 2023.2.1 should now target the E70ES1 device.
      • For Avant products, this release supports targeting of silicon based on their release status. Refer to the following table for details.
        2024.1 Designator Status Prior Designator
        E70ES1 Engineering Sample E70
        E70 Early Access NA
  • Tool and Other Enhancements
    • Bitstream
      • The IDCODE of LFD2NX-28 and LFD2NX-9 devices have been updated. Due to these changes, regenerating the bitstream is recommended.
    • Foundation IP
      • In the Lattice Avant PLL Module configuration interface, when Enable Dynamic Phase Ports is checked, a Use Phase Advance option is added. When this is enabled, the maximum VCO frequency is reduced. Otherwise, the value remains at 4 GHz.
      • Lattice Avant MPP enables 5G and base video protocols, which include SyncE and DP/eDP.
    • Soft IP
      • By default, the IP on Server and IP Catalog options to “Show latest IP Version only” and “Show IP supported by target device only” are now enabled.
    • Programmer – The Verify Public Key operation has been added to Radiant Programmer.

Radiant 2024.1

  • Radiant Installer
    • A new version of the Radiant installer has been uploaded to the Lattice website. Installing the latest 2024.1.0.34.2 version is recommended if you are currently using the 2024.1.0.34.1 version or older.
    • Installation Instructions
      Refer to the list below for the instructions to install the new version of the Radiant software. Also ensure that no instances of Radiant are running before attempting to install the new version.
      • To install the new version on Windows:
        1. Extract the zip file and navigate to the location where you want to save it.
        2. Double-click the 2024.1.0.34.2_Radiant.exe file to install the software.
      • To install the new version on Linux:
        1. Extract the zip file and navigate to the location where you want to save it.
        2. Execute the Radiant run file as follows:
          % cd <directory_with_RUN>
          % ./ 2024.1.0.34.2_Radiant_lin.run
      If you are using Lattice Radiant 2024.1 (2024.1.0.34.1), refer to the instructions below.
      • To install the new version on Windows:
        1. Uninstall Lattice Radiant 2024.1 (2024.1.0.34.1).
        2. Extract the zip file and navigate to the location where you want to save it.
        3. Double-click the 2024.1.0.34.2_Radiant.exe file to install the software.
      • To install the new version on Linux:
        1. Uninstall Lattice Radiant 2024.1 (2024.1.0.34.1).
        2. Extract the zip file and navigate to the location where you want to save it.
        3. Execute the Radiant run file as follows:
          % cd <directory_with_RUN>
          % ./ 2024.1.0.34.2_Radiant_lin.run
  • Device Support:
    • Lattice Avant™ (LAV-AT)
      • E70ES1 (-1/-2/-3) 0.82V (COM/IND) – LFG676, CSG841, LFG1156
      • Designs targeting the E70 device in 2023.2 or 2023.2.1 should now target the E70ES1 device.
      • For Avant products, this release supports targeting of silicon based on their release status. Refer to the following table for details.
        2024.1 Designator Status Prior Designator
        E70ES1 Engineering Sample E70
        E70B Production NA
        E70 Early Access NA
    • Certus™-NX (LFD2NX)
      • 9K (-7/-8/-9) 1.00V (COM/IND) – CSFBGA121
      • 28K (-7/-8/-9) 1.00V (COM/IND) – CABGA196, CABGA256, CSFBGA121
  • Tool and Other Enhancements:
    • License
      • The version of Lattice license FlexNet utility and license daemon has been upgraded to v11.19.4.1.
      • The new “LSC_RADIANT_3” RTL encryption key has been added to Radiant to prevent the encrypted RTL in 2024.1 from being used in earlier versions of Radiant.
    • Radiant Installation Wizard
      • The LATTICE_LICENSE_FILE and SALT_LICENSE_SERVER environment user variables have been added to the installation page.
    • The default Flexnet variable LM_LICENSE_FILE is now displayed on the installation page.
  • Foundation IP
    • JESD204B support has been added for the CertusPro-NX (LFCPNX) device.
    • The IP on Server tab in Radiant has been updated to support publishing of third-party IP.
  • Strategies
    • The “Read Write Check on RAM” LSE strategy has been added to Radiant strategy settings for Nexus and Avant devices.
    • Impose Hold Timing Correction strategy has been added to the Radiant Place & Route strategy settings.
  • Block-Based Design
    • The Block-Based Design feature now supports Lattice Synthesis Engine (LSE).
    • Isolation Design Flow has been added to Block-Based Design. This new feature allows you to create prohibited regions that excludes any logic or routing from the rest of the design.
  • Design Rule Checking – DRC has been updated to generate a report which specifies any combinational loops or clocks that have been identified and connected to black box modules.
  • Simulation
    • Radiant software now includes QuestaSim™ Lattice OEM Edition for simulation, debugging, and verification processes. The ModelSim simulator has been replaced by this new tool.
    • Since QuestaSim is a 64-bit application, it can support designs whose memory usage is greater than 4GB during simulation.
  • Power Calculator
    • Watt values in Power Calculator reports are rounded off to 3 digits after the decimal point.
    • When using Avant, the Power Screen field is available for selecting power screen options based on device license.
  • Disable Message Tcl Command – Warning and info messages can now be disabled using the msg_disable Tcl command.
  • Programmer – “Verify feature row” and “Verify lock policies” operations for generating VME have been added to Programmer.
  • Reveal
    • Reveal Inserter provides the option to choose between the standard RTL (Pre-Synthesis) and the Post-Synthesis debug flows. Post-synthesis debugging allows easier monitoring of debug signals and the insertion of debug logic after a design has been synthesized.
    • Configuring User Memory Setup section has been updated.
    • When debugging a JTAG chain, bypass instruction can be used to select or isolate specific devices to debug or to skip.
    • In the Eye Diagram interface, “Unit Interval” has been changed to “Phase Step” and “Voltage” has been changed to “Vertical Step”.
  • IP Packager – New Tcl commands have been added for IP Packager.
  • Export Files – Gate-level simulation and IBIS files are set to “Disabled” by default in creating a new project.
  • Tool Options – Centralized management for individual and group settings is now supported in Tool Options.
  • Timing Constraints
    • The Timing Analyzer now supports set_false_path -setup and -hold options.
    • Generated clocks now include -add and -master_clock parameters.
  • Timing Tcl Commands
    • All sta_report_timing commands now support the -file and -app options. The -file command saves the result to a file whose name is provided after the -file option, and the -app flag informs the command to append the report instead of overwriting the file.
  • Hardware Data File
    • The DDR delay code settings has been updated for the MachXO5-NX (LFMXO5) device.
    • CertusPro-NX (LFCPNX)
      • Differential 100ohm termination for input differential IO types has been added to the CertusPro-NX (LFCPNX) .ibs file.
      • On-die termination (ODT) support for input and bidirectional models have been fixed for CertusPro-NX (LFCPNX) IBIS models.
    • Hard DPHY now captures the rising edge of the byte clock of u_txwordclkhs (UTWDCKHS).

Radiant Update 2023.2.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 50K (-9/-8/-7) 1.0V (AUTO) – ASG256, CBG256, BFG484.
  • Tool and Other Enhancements:
    • Primitives
      • OUTDELAYC primitive has been added for CertusPro-NX device.
    • Device Constraint Editor
      • 75Mhz selection has been added for MCCLK_FREQ.
    • MAP – DRC errors regarding shared configuration pin usage for Nexus devices have been resolved.
    • Timing Data – DPHY timing arcs to fix unconstrained path have been updated for Nexus device.
    • Reveal
      • JTAGhub feature modules have been enhanced for Nexus and Avant devices.
      • Pooling of data while SEDC is running has been enhanced for Reveal Controller and Reveal Analyzer.
    • Hardware Data File
      • Minimum pulse width (MPW) has been aligned with datasheet for CrossLink-NX device.
      • Correlation for CertusPro-NX (LFCPNX) IBIS Model has been resolved.

Radiant 2023.2

  • Device Support:
    • Lattice Avant™ (LAV-AT)
      • E70 (-1/-2/-3) 0.82V (COM/IND) – LFG676, LFG1156
        • 500E has been renamed to E70.
    • CrossLink™-NX (LIFCL)
      • 33U (-7/-8) 1.00V (COM/IND) – FCCSP104
      • 33U (-8) 1.00V (COM/IND) – WLCSP84
  • Tool and Other Enhancements:
    • Device Selector – The device information of the LAV-AT device (E70) has been updated to add 637000 System Logic Cells (LCs).
    • Lattice Synthesis Engine (LSE) – LSE now supports the LAV-AT device.
    • Foundation IP – LAV-AT-E design needs to be re-generated for the Foundation IP/Soft IP. You also need to re-compile the design and re-generate the bitstream.
    • Primitives – The following primitives have been added for the LAV-AT device:
      • DDRPHY64C and DDRPHY72C
      • DDRPHY16D, DDRPHY32D, and DDRPHY64D
      • DDRPHY16E, DDRPHY32E, and DDRPHY64E
      • CONFIG_DONE and CONFIG_LMMIC
      • ECLKDIVA and ECLKSYNCA
      • OSCE
    • GPIO Pins – For the LAV-AT device, each HPIO banks now have 1 EXT_RES dedicated pins.
    • IBIS Models – IBIS has been enhanced to include sysCONFIG pins for the LAV-AT device.
    • Third-Party Simulation Tools – Cadence Xcelium and Synopsys VCS now support the LAV-AT device.
    • MAP – For all Nexus devices, mapper issues DRC if ECLKSYNC is missing from the ECLKDIV input.
    • Place & Route Timing Analysis – Running PAR Timing Analysis is now required for Nexus devices.
    • Static Timing Analyzer (STA) – The STA introduces automated multi-corner Static Timing Analysis reporting to all Nexus devices which eliminates manual operations.
      • While the PAR report includes multi-corner timing, it is recommended to run STA and analyze the timing results at each corner in the STA timing report.
    • CDC Register – The CDC_register attribute allows you to constrain CDC (Clock Domain Crossing) synchronization registers for placement and timing analysis.
    • SEI Editor – The multi-bit (2-bit) error option has been added to the SEI Editor for all Nexus devices.
    • Programmer
      • To enable a robust Dual Boot and Ping-Pong functionality, the bitstream of LFMXO5-25, LFMXO5-55T, and LFMXO5-100T devices with embedded flash memory needs to be re-generated.
      • Deployment Tool now allows adding user data while generating Dual Boot and Ping-Pong features.
    • Strategies – The default value of the GSR Infer strategy has been changed to “OFF” for Synplify, LSE, and MAP.
    • Block-Based Design – The Exclusive option has been added to Physical Designer for reused macros.
    • IP Generator – The IP Generator has been enhanced to be able to provide VHDL top-level file capability.
    • License File – The TS_OK option has been enabled for Radiant subscription license. This option allows you to run the Radiant software on a remote connection.
    • File List – In File List View, you can now manually set top-level modules by right-clicking on an input file.
    • Inclusive Language – Radiant documentation has been partially updated to follow Lattice’s Inclusive Language guidelines.
      • The following terms have been updated:
        • Master SPI has been changed to Controller SPI.
        • Slave SPI has been changed to Target SPI.
    • Simulation Wizard
      • Simulation Wizard now supports the "-t" option. This option has been added to specify the time resolution of the simulator for VHDL resolution in mixed-language simulations.
      • The “sim_generate_script” Tcl command has been added for Simulation Wizard. You can use this command to generate any file types from your current Radiant project.
    • TCL Enhancement – New Tcl commands have been added to support project and non-project flows.
      • STA Tcl commands have been added allowing you to query the timing database and generate timing reports or data without having to recompile the design.
    • Test Fixture Template – The GSR instance has been added to the Test Fixture Template for Avant and Nexus devices.

Radiant Update 2023.1.1

  • Tool and Other Enhancements:
    • PLL Foundation IP – The Fractional-N settings were updated to improve PLL design stability for all Nexus devices.

Radiant 2023.1

  • Device Support:
    • MachXO5™-NX (LFMXO5)
      • 55T (-7/-8/-9) 1.00V (COM/IND) – BBG400
      • 100T (-7/-8/-9) 1.00V (COM/IND) – BBG400
  • Tool and Other Enhancements:
    • Block-Based Design – The Block-Based Design feature has been added to the Radiant software. This new feature allows you to implement macros in your project, including the ability to export macros and reuse them in other designs.
    • Message Classification – The “Critical Warning” message severity level has been added to the Radiant software. This severity level pertains to issues that could result in a functional problem.
    • Multi-thread Route – The multi-thread route has been added to the Radiant software for the Avant device. You can now run PAR in multi-thread mode by using the "-exp maxThreads=n" command. The default number of threads in the Avant device is 4, and the maximum is 8.
    • Place & Route Timing Analysis – The Place & Route Timing Analysis process has been updated for Avant and other devices. Running PAR Timing Analysis is required for Avant, while it is optional for other devices.
    • Programmer – Support for MachXO3D and LFMNX devices have been added to the Programmer tool.
    • Reports View – The Constraint Checker Report section has been added to the Synthesis Reports tab of the Radiant software. This section is only visible when Synplify Pro is used.
    • Reveal Controller – The implementation of Reveal Controller for Hard IPs has been updated for Radiant 2023.1.
    • Revision Control – Radiant will now output a list of files that are recommended to be placed under revision control for the current project.
    • Strategies – The Command Line Option strategy has been added to Place & Route Timing Analysis to enable the false_path constraint for timing constraints coverage.
    • sysCONFIG Settings – With this update, at least one of JTAG_PORT, SLAVE_SPI_PORT, SLAVE_I2C_PORT, or SLAVE_I3C_PORT must be enabled for Nexus devices. Otherwise, Map reports a DRC error.
    • Synthesis Tool – The default synthesis tool for new projects has been changed to Synplify Pro.
    • Timing Analysis Report – The Timing Analysis Report has been updated for the Avant device. The DELAYB calculation is now included in the data path.
    • Timing Data – The IOLOGIC GBB timing data for the CertusPro-NX device has been updated for Radiant 2023.1.

Radiant Update 2022.1.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 50K (-7/-8/-9) 1.00V (COM/IND) – ASG256
      • 50K (-7/-8/-9) 1.00V (COM/IND) – BBG484
      • 50K (-7/-8/-9) 1.00V (COM/IND) – BFG484
      • 50K (-7/-8/-9) 1.00V (COM/IND) – CBG256
  • Tool and Other Enhancements:
    • Power Calculator – The Power Calculator for CertusPro-NX (LFCPNX) has been updated to reflect a roughly 10% improvement (lower power consumption) for designs using PCIe over previous versions due to improved silicon correlation data.
    • Reveal Logic Controller/Analyzer – The Reveal User Status and User Control Register features have been updated to expand the values of the control and status signals to 32-address locations with a maximum data-width of 8 bits.
    • Simulation Library – The Simulation Library has been updated to include compilation of PMI and source libraries.

Radiant 2022.1

  • Device Support:
    • Lattice Avant™ (LAV-AT-E)
      • 500K (-1/-2/-3) 0.82V (COM/IND) – LFG676
      • 500K (-1/-2/-3) 0.82V (COM/IND) – LFG1156
      • GSR is not available for the LAV-AT-E device.
    • The license maintenance number has been updated to support the current Radiant software’s version number. Please visit the Lattice Software Licensing page to request for a new license. To check the license maintenance number, open the Radiant license file located in ..\<install_directory>\license.
    • CrossLink™-NX (LIFCL)
      • SGMIICDR primitive is not supported in LIFCL (40K/17K) WLCSP72 and QFN72 packages.
      • The -7 speed grade option has been removed from the LIFCL-33 device.
  • Tool and Other Enhancements:
    • FPGA Libraries – The FPGA Library Guide has been updated to include the LAV-AT-E device.
    • Netlist Analyzer – The Netlist Analyzer tool now supports post-synthesis schematic view for Synplify Pro.
    • PAD Specification File – The PAD report has been updated to include the complete IO properties information of device families.
    • PLL Foundation IP – The PLL parameter calculation script has been updated to optimize the tuning algorithm for all devices except the iCE40UP and LAV-AT-E device.
    • Pre-Synthesis Constraint Editor (previously Timing Constraint Editor) – The Pre-Synthesis Constraint Editor tool has been updated to support the set_max_skew constraint for the Radiant 2022.1 software.
    • Programmer – The Programmer tool has been updated to support the LAV-AT-E device.
    • Project Navigator – The Message Promotion/Demotion option has been added to Project > Message Promotion/Demotion. This new feature allows you to use TCL commands to promote/demote a message if you do not want it to be visible in non-GUI mode.
    • Reports
      • The MAP Resource Usage section has been updated to display the Logic, Distributed RAM, and RIPPLE Logic information of the project.
      • Constraint Propagation section has been added to Synthesis Reports.
      • Constraint Summary has been added to the Post-Synthesis and MAP Reports.
    • Timing Analysis Reports – The Timing Analysis Reports format has been updated to include the following sections:
      • The “Setup at User Specified Speed Grade Corner at Minimum Degrees” section has been added to the PAR Timing Analysis Report for the LAV-AT-E device.
      • A new command line parameter -dump_uncovered has been added for the PAR Timing Analysis Report. This results in timing dumping connections that are not covered in the uncoveredConn.log file.
    • Reveal Logic Controller/Analyzer
      • The User Memory, User Control, and User Register options have been added to the Reveal Logic Controller/Analyzer tool.
      • The Reveal Controller tool has been updated to add the simulation model feature.
      • For the LAV-AT-E device, adding the PAR Strategy command line option, “-exp WARNING_ON_PCLKPLC1=1” when using Reveal and JTAGH25 is required to avoid errors.
    • SSO Calculator – The SSO Calculator has been updated to support the LAV-AT-E device.
    • Synthesis Tool – The Synthesis default option has been added to Tool > Options. In the dropdown menu, you can choose between Lattice LSE or Synplify Pro.

Radiant Update 3.2.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 100K (-7/-8) HP/LP 1.0V (AUTO) – ASG256
      • 100K (-7/-8) HP/LP 1.0V (AUTO) – BBG484
      • 100K (-7/-8) HP/LP 1.0V (AUTO) – CBG256

Radiant 3.2

  • Device Support:
    • MachXO5™-NX (LFMXO5)
      • 25K (-7/-8/-9) HP/LP 1.0V (COM/IND) – BBG256
      • 25K (-7/-8/-9) HP/LP 1.0V (COM/IND) – BBG400
    • CrossLink™-NX (LIFCL)
      • 33K (-7/-8) HP/LP 1.0V (COM) – WLCSP84
      • 33K (-8) HP/LP 1.0V (IND) – WLCSP84
  • Tool and Other Enhancements:
    • License Debugger – The License Debug tool now displays all Network Feature Card (NIC) IDs. A direct link to LmTools has also been added to access the license server.
    • Power On Reset (POR) Debug – This new feature has been added to the Reveal Analyzer/Controller tool for the Radiant 3.2 software.
    • Programmer, Reveal Logic Analyzer/Controller, SEI Editor
      • These tools have been updated to support the MachXO5-NX (LFMXO5) and CrossLink-NX (LIFCL-33) devices with bitstream generation capability and full encryption/ authentication.
      • Added I3C Bridge support to Programmer.
    • Radiant File Type Support – The "Force File Type" option has been added to the “Add Existing File” dialog box. This new feature allows users to change their file types to Verilog or VHDL.
    • Radiant Project File – The Radiant Project (.rdf) file has been updated to include the Radiant version number.
    • Simulation Wizard – The Simulation Wizard tool has been updated. Users can now specify the simulation run length if the “Run simulation” option is selected.
    • Timing Analyzer – The “-datapath_only” option has been added to the set_max_delay constraint

Radiant 3.1.1 MachXO5-NX Device Update

  • Device Support:
    • MachXO5™-NX (LFMXO5)
      • 25k (-7/-8/-9) HP/LP 1.0 V (COM/IND) – BBG256
      • 25k (-7/-8/-9) HP/LP 1.0 V (COM/IND) – BBG400
  • Tool and Other Enhancements:
    • Programmer – The Programmer tool has been updated to support the MachXO5-NX (LFMXO5) device with plain bitstream only, no security or encryption features.
    • Reveal Logic Analyzer – The Reveal Logic Analyzer tool has been updated to support the MachXO5-NX (LFMXO5) device.
    • Update installer allows user to specify installation path – The user can specify the installation path when installing the MachXO5-NX Device Update

Radiant Update 3.1.1

  • Device Support:
    • CertusPro™-NX (LFCPNX)
      • 100K (-7/-8/-9) HP/LP 1.0 V (COM/IND) – BFG484
      • 100K (-7/-8/-9) HP/LP 1.0 V (COM/IND) – CBG256
      • Available under subscription licensing
    • Certus™-NX-RT (UT24C)
      • 40K (-7) HP/LP 1.0 V (AUTO) – CABGA256 is license controlled
    • CertusPro™-NX-RT (UT24CP)
      • 100K (-8) HP/LP 1.0 V (IND) – BBG484 is license controlled
  • Tool and Other Enhancements:
    • Radiant Device Selector – UT24C and UT24CP OPNs (Ordering Part Number) have been added to the Device Selector for the RT (Radiation Tested) Devices.

Radiant 3.1

  • Device Support:
    • Certus™-NX Auto Device PSR (LFD2NX)
  • Tool and Other Enhancements:
    • Device Constraint Editor – The default configuration of JTAG_PORT, DONE_PORT, INITN_PORT, and PROGRAMN_PORT has been set to “ENABLE.”
    • IO Eye-Opening Monitor (IO EOM) – The IO EOM feature has been added to the Reveal Analyzer/Controller tool for devices with PCS hard IP such as LFCPNX device family.
    • IP Encryption Flow – Improved protection for IEEE1735 compliant IP Encryption Flow.
    • IP Packager – The IP Packager tool has been updated. Radiant software now uses the Propel software version of IP Packager.
    • JTAG Debug – This new feature has been added to support simultaneous debugging of processor system and Reveal hardware debugging.
    • Standalone Timing Analyzer – This new feature can be used to run experimental timing analysis on designs using post-synthesis, post-map, post-PAR Unified Design Database (.udb), and associated timing constraints specified in the .pdc file of the design. The Standalone Timing Analyzer content has been added to the Radiant Software Help.
    • VHC File Extension Support – This release of the Radiant software adds the ability to recognize files with the .vhc file extension as VHDL files. VHC files inherit the same characteristics as .vhd (VHDL) files.
    • Virtual IO Ports Support – This new feature allows easy timing/resource estimation for over exceeding IO designs. A “Virtual” column has also been added to the Device Constraint Editor.

Radiant 3.0

  • Device Support:
    • CertusPro™-NX Device Family (LFCPNX):
      • 100K (-7/-8/-9) HP/LP 1.0V (COM/IND) - ASG256
      • 100K (-7/-8/-9) HP/LP 1.0V (COM/IND) - BBG484
      • 100K (-7/-8/-9) HP/LP 1.0V (COM/IND) - LFG672
      • 100K devices bitstream enabled
  • Tool and Other Enhancements:
    • Device Selector – When creating a new project in the Radiant software, the Device Selector now defaults to LICFL (CrossLink-NX), Performance Grade: 9_High-Performance_1.0 V, Part Number: LICFL-17-9BG256C. Also, the Device Selector now shows both device Part Name and device Family Name in the Family list. For example: LIFCL (CrossLink-NX).
    • FPGA Libraries – FPGA Libraries have been added for the CertusPro-NX Device Family (LFCPNX).
    • License Debug – Added license debug capability to specify the location of the license file and show the features that are available with the license in the Help > License Debug menu.
    • Security Settings Tool – The Security Settings Tool now supports .pem and .der file formats.
    • Signal Traceability – This new feature allows you to trace signals from Report View and Output Window and display signals in Netlist Analyzer.
    • Tutorial – The Lattice Radiant 3.0 Tutorial with CrossLink-NX (LIFCL) adds support for the newest CrossLink-NX Evaluation Board, Revision B. Tasks for programming the chip and for on-board logic analysis have been added.
    • Unified Constraints and Timing Analysis Flow – Pre-synthesis Timing Constraints Editor now works for both Lattice Synthesis Engine (LSE) and Synplify Pro.

Radiant Update 2.2.1

  • Device Support:
    • CrossLink-NX Automotive Devices (LIFCL):
      • 17K (-7) HP/LP 1.0V – CSFBGA121
      • 17K (-7) HP/LP 1.0V – CABGA256
      • 40K (-7) HP/LP 1.0V – CSFBGA121
      • 40K (-7) HP/LP 1.0V – CABGA256
      • 17K and 40K devices bitstream enabled.
    • CrossLink-NX (LIFCL) & Certus-NX (LFD2NX) PSR for C/I
  • Tool and Other Enhancements:
    • Power Calculator – Updates have been added to I/O, MIPIDPHY, and PCIE.
    • Mentor ModelSim Lattice Edition – ModelSim Lattice Edition has been updated to Revision 2021.02

Radiant 2.2

  • Device Support:
    • CrossLink-NX Device Family (LIFCL)
      • 17K and 40K devices bitstream enabled.
    • Certus-NX Device Family (LFD2NX):
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA196
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSFBGA121
      • 40K devices bitstream enabled
  • Tool and Other Enhancements:
    • Programmer – Supports full encryption and authentication
    • Simulation tool change – Mentor ModelSim® is the new OEM simulation tool included with Radiant software. ModelSim replaces Aldec-Active HDL™.
              NOTE: For post-routing simulation, please use a full version of ModelSim PE. The OEM version will be addressed in an upcoming software release
    • Reveal – Reveal Analyzer/Controller support for CrossLink-NX (LIFCL) and Certus-NX device families.
    • Soft Error Injection – Soft Error Injection (SEI) Editor allows you to generate single-bit errors, insert them into a bitstream, and detect them for analysis, simulating the effect of radiation damage on the device’s configuration memory./li>

Radiant 2.1

  • Device Support:
    • Certus™-NX Device Family (LFD2NX) offers the following 40K device:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream Disabled
        • CABGA256
      Note: Bitstream generation is disabled for CrossLink-NX devices for this release, but bitstream for LIFCL-40K is expected to be enabled in the upcoming Service Pack (Radiant 2.1 SP1).
  • Tool and Other Enhancements:
    • Physical Designer – The Physical Designer provides a central location where a user can do all the floor-planning and be able to view the physical layout of the design.
    • FPGA Libraries -- New Primitives:
      • CRE (LFD2NX) only. License controlled.)
      • FIFO16K
    • Pin Migration - This release adds Pin Migration support, allowing user to view devices that are of the same family and package as your current device and view incompatible pins.
    • Security – The LFD2NX device supports user mode Cryptographic Engine (CRE).
    • SystemVerilog Support – as follows:
      • Lattice Synthesis Engine – The ability to read and synthesize SystemVerilog.
      • File Hierarchy View – The ability to read and produce a hierarchical file view of design.
      • Hierarchy Viewer – The ability to read and produce hierarchical view in Design Constraint Editor, Netlist Analyzer, Floorplan View.
      • Reveal – support for SystemVerilog for Reveal Controller, Reveal Analyzer, and Reveal Inserter.

Radiant Update 2.0.1

  • Device Support:
    • CrossLink-NX™ Device Family offers new 17K devices and adds new 40K packages:
      • 17K (-7/-8/-9) HP/LP 1.0V (COM/IND) – Bitstream disabled
        • CABGA256
        • CSFBGA121
        • QFN72
        • WLCSP72
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND)
        • CSFBGA121
        • CABGA256
  • Tool and Other Enhancements/Updates:
    • IP Evaluation for CrossLink-NX 40K devices – If you don’t have licenses for the soft intellectual properties (IPs) downloaded from “IP on Server,” you can evaluate these soft IPs for approximately four hours before the device resets itself.
    • New Foundation IPs - Four new foundation IPs are added:
      • 1D Filter
      • Adder Tree
      • Barrel Shifter
      • DSP_Mult_Mult_Accumulate
    • Programmer – Programmer has enhanced support for the Security features including Flash protection (128-bit device password) and AS-256 Encryption and Lock.
    • Security Tools (Key Generation) – A new Radiant Bitstream Security Setting tool has been added that allows you to generate and verify keys that are used for bitstream obfuscation. The GUI provides user entry for Flash protection (128-bit device password) and AES-256 Encryption.
    • sysCONFIG – A new attribute, CONFIGIO_VOLTAGE_BANK0/1, has been added for sysCONFIG.
    • Updated Radiant Tutorial for CrossLink-NX – An updated Tutorial has been added using the CrossLink-NX Evaluation Board.

Radiant 2.0

  • Device Support:
    • CrossLink-NX Device Family for the following packages:
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CABGA400
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - CSBGA289
      • 40K (-7/-8/-9) HP/LP 1.0V (COM/IND) - QFN72
      The Lattice Radiant Software Guide for Lattice Diamond Users has been enhanced to help users to migrate their designs to CrossLink-NX devices using the Radiant software. Users with designs on such Lattice devices as CrossLink and ECP5, designed using Lattice Diamond software, can use this guide to quickly grasp concepts of the new features of CrossLink-NX devices and designing with the Radiant software.
  • Tool and Other Enhancements:
    • Device Constraint Editor – Updates and enhancements have been added to Device Constraint Editor.
    • ECO Editor – A new Radiant software tool has been added that supports interactive Engineering Change Order (ECO) editing.
    • Floorplan View – Updates and enhancements have been added to Floorplan View. Updates include a new I/O placement feature that is used for I/O assignment such as DDR interface, DQS and clock assignments.
    • IP Catalog – Updates and enhancements have been added to Modules.
    • Power Calculator – Updates and enhancements have been added to support CrossLink-NX devices.
    • Propagation of IP Constraints – Radiant software now supports hierarchical constraints in IP applications and writes a new constraint file to propagate lower level constraints to top level under predefined constraint design rules.
    • Reveal Controller – A new Radiant software tool has been added for the CrossLink-NX family to create virtual control switches/LEDs; reading/writing to bank of registers/memory; and read/write access to control and status registers of PLL, I2C/FIFO, DPHY, CDR and PCIe hard-IPs.
    • Run Manager – A new Radiant software tool has been added that is used to run multiple synthesis and place and route passes, compare the results of multiple implementations for further analysis to get best solutions.
    • Source Templates – New CrossLink-NX templates have been added for both Verilog and VHDL in Source Template. In Source Template Editor, see:
      • Verilog > Primitive Templates > lifcl Primitive
      • VHDL > Primitive Templates > lifcl Primitive
    • Simultaneous Switching Outputs (SSO) Calculator – A new Radiant software tool has been added that estimates Simultaneous Switching Noise (SSN) affecting a victim pin according to the switching characteristics of aggressor pins.
    • Timing Constraint Editor – Updates and enhancements have been added to Timing Constraint Editor.

Radiant 1.1

  • iCE40 UltraPlus device enhancements and bug fixes
    • New HDL attribute RGB_TO_GPIO.
    • Four new iCE40 UltraPlus bitstream strategy options have been added:
      • Enable Warm Boot
      • Set All Unused IO No Pullup
      • Set NVCM Security
      • SPI Flash Low Power Mode
  • Enhanced Intellectual Property (IP) tools and flow
  • Constraints Syntax and Flow updates
    • Timing Constraints: Added Object Access Command (-of_objects) support which allows flexible and efficient object accesses. Note that this option is supported in constraint files only in Radiant software 1.1. Graphical User Interface support for this option is expected in Radiant 1.2.
    • Physical Constraints: Added -region option support in ldc_prohibit constraint. This option is also supported in ldc_set_location.
    • Timing Constraint Editor:
      • Added set_load constraint
      • Added Disable/Enable checkbox that allows you to easily disable or enable constraints.
  • Tool and Other Enhancements
    • Cross-probe timing path from timing reports. Map and PAR timing reports now have hyperlinks that allow users to view timing paths in Netlist Analyzer, Physical View, and Floorplan View.
    • Detachable Tool Windows. Detach and attach functionality has been added for all tools and views, allowing user to work on a tool outside of the Radiant software environment.
    • Lattice Synthesis Engine (LSE). LSE has significant performance improvements from Radiant software 1.0 including:
      • Improvements in embedded block RAM (EBR), finite state machine (FSM), and digital signal processor (DSP) extraction.
      • Improvements in Area implementation and run time.
    • Power Estimator. A new stand-alone Power Estimator has been added.
    • Simulation Wizard. The Simulation Wizard has been updated to support post-synthesis simulation.
    • Source Template. A new Source Template tab has been added to make it easier to access various templates without the need to have the Source Editor running. The selection of templates has been enhanced. Available templates, in both VHDL and Verilog, include:
      • Common Templates
      • PMI Templates
      • Primitive Templates
      • Attribute Templates
      • Encryption Templates
      • Timing Constraints
      • Physical Constraints
    • Ubuntu operating system. Support for Ubuntu operating system LTS 16.4 has been added

Radiant 1.0 SP1

  • Re-compile with this service pack if users uses the LVDSE IO type in their design.
  • If CCU2 primitives are indicated in the Area Report of the LSE synthesis report file, there is a chance of getting an incorrect synthesis result from carry chain optimizations. It is advised to re-compile the design using this service pack to avoid a simulation and/or hardware operation failure. This fix is applicable for LSE only.
  • Fixed several other key customer defects resolving instability relating to map, place and route in the timing engine.

Radiant 1.0

  • Standardized Timing and Physical Constraints utilizing the popular SDC format to help you easily apply constraints to your designs.
  • Unified Static Timing Analysis from Synthesis to Place & Route to accelerate design timing closure.
  • Enhanced IP Security Flow and Ecosystem to allow efficient distribution of Soft IP’s and to improve 3rd Party Soft IP security.
  • New and Simplified GUI design with option of light or dark color theme.
  • Simplified and Efficient Design Flows and Tools to improve Ease-of-Use.

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