PCIe for Nexus FPGAs: Does the vc_tx_valid_i can be delayed (insert 3 clock cycles) during long external memory read since the FPGA lose the access for some clocks?
Description: The vc_tx_valid_i should not be delayed or do insertion of the 3 clock cycles gap within packets as it affects the validity of the data thus it is forbidden to insert such delay. This cannot be use as a workaround for the long external memory read process.
Solution:
Alternatively, users can use DMA or FIFO buffer to interface with the external memory.