It is not advisable to perform gate level simulation for the PCIe Demo designs from the PCIe Development kit. The reasons are below:
- There are several signals that must be forced for the link to come up. Locating these signals in the gate level netlist can be difficult due to synthesis optimization and/or net renaming.
- One of the signals to be forced (no_pcie_train) is implemented as a internal signal in the design. The signal is optimized out for some level of the hierarchy.
- There are multiple timers in the design per PCI Express requirement. These cannot be sped up for gate level simulation so simulation time of at least tens of milliseconds is required to bring the link up.
- Multiple simulation iterations are likely required to bring up the gate level simulation environment.
As the Demo Design works in hardware, the recommended method for observing transactions at the user interface is via Reveal, Lattice on-chip debugger.