文章详情

ID: 1501
实例类型: faq
分类: Device Programming
相关: Configuration/Programming
产品系列: LatticeXP2

搜索答案数据库

Search Text Image

ispLEVER / ispVM System: Why does it take 4 minutes to program the XP2 FPGA device with the svf file generated by ispVM System software?

The official SVF standard does not support the looping and polling commands necessary to do a faster erase. In order to remain compatible with third party tools, we must use the worst case delay.


Our SVF interpreter supports looping and status polling, so the SVF file can be modified by hand to use these commands. If user do this, it will run much faster but won't be compatible with third party software.


For example:


RUNTEST             IDLE       3 TCK     2.40E+002 SEC;


Can be changed to:


LOOP 2400 ;


RUNTEST             IDLE       3 TCK     1.00E-001 SEC;


SDR        1              TDI  (0)


                               TDO  (1);


ENDLOOP ;


However, most 3rd-party vendors only support the SVF standard.


For customers who require 3rd-party support and fast erase and programming times, we recommend using STAPL instead of SVF. STAPL supports the looping and status polling algorithm.