Lattice QSPI to NXP MPU Interface Reference Design

NXP i.MX 93 MPU to Lattice ECP5 FlexSPI Low-latency Interface Solution

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Lattice Semiconductor and NXP have collaborated to deliver this reference design, complete with source code, to end customers. This solution is designed to facilitate the implementation of FlexSPI communication and to expedite deployment using the Lattice ECP5 Evaluation Board. The i.MX 93 processor enables high-performance, low-latency communication with FPGA/CPLD devices via FlexSPI interfaces.

Features

  • Supports 1/2/4/8 bidirectional data lines
  • Supports SDR/DDR at maximum of 200MHz
  • Simple timing implementation at FPGA/CPLD

NXP and Lattice

 

Block Diagram

Ordering Information

Documentation

技术资源
标题 编号 版本 日期 格式 文件大小
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Lattice QSPI to NXP MPU Interface Reference Design - Source Code
2/11/2025 ZIP 130.3 KB