The Lattice Semiconductor RISC-V AHB-L IOPMP (I/O Physical Memory Protection) IP is a separate physical memory protection unit that prevents illegal or unexpected access to some specific regions. These regions can be accessed by the RISC-V CPU but should not be accessed by some controllers, such as Direct Memory Access (DMA) or Ethernet. The RISC-V AHB-L IOPMP IP includes three AHB-Lite interfaces. The AHB-Lite control interface connects to the memory-mapped control and status registers while the two data interfaces bridge for the data path. The control path justifies the accessibility based on the address and entry settings. It decides whether or not to block this access, raise an interrupt, and respond with errors when the access is illegal.
Resource Utilization details are available in the IP Core User Guide.