CSI-2/DSI D-PHY Transmitter IP Core

Convert Parallel Formatted Data Streams to MIPI CSI-2/DSI

Related Products

The Lattice Semiconductor CSI-2/DSI D-PHY Transmitter IP Core converts data bytes from a requestor to either DSI or CSI-2 data format for the Lattice Avant™, Nexus™, and Nexus 2 platforms. The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for applications that require a D-PHY transmitter in the FPGA logic.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with MIPI D-PHY v2.1, MIPI DSI v1.3, and MIPI CSI-2 v1.2 specifications.
  • Supports 1, 2, 3, or 4 MIPI D-PHY data lanes.
  • Supports DSI video modes.
  • Supports low-power (LP) mode during vertical and horizontal blanking.

Jump to

Block Diagram

CSI-2-DSI-DPHY-TransmitterExpand Image

Ordering Information

IP core is available for FREE for use in Lattice Diamond design software. Please refer to the below Ordering Part Numbers for the Lattice Radiant design software.

Device Family Part Number
Single Seat Annual Single Seat Perpetual
CrossLink-NX DPHY-TX-CNX-US DPHY-TX-CNX-UT
Certus-NX DPHY-TX-CTNX-US DPHY-TX-CTNX-UT
Certus-N2 DPHY-TX-CN2-US DPHY-TX-CN2-UT
CertusPro-NX DPHY-TX-CPNX-US DPHY-TX-CPNX-UT
Avant-E DPHY-TX-AVE-US DPHY-TX-AVE-UT
Avant-G DPHY-TX-AVG-US DPHY-TX-AVG-UT
Avant-X DPHY-TX-AVX-US DPHY-TX-AVX-UT
MachXO5-NX DPHY-TX-XO5-US DPHY-TX-XO5-UT
Bundled MIPI-BNDL-US MIPI-BNDL-UT

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Transmitter Submodule IP - Lattice Diamond Software
FPGA-IPUG-02024 1.6 5/14/2021 PDF 2.3 MB
CSI-2/DSI D-PHY Transmitter IP Core - User Guide
FPGA-IPUG-02080 2.4 6/26/2025 PDF 2.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Transmitter IP Core - Release Notes
FPGA-RN-02041 1.1 6/26/2025 PDF 221.1 KB

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