CSI-2/DSI D-PHY Receiver IP Core

Convert MIPI CSI-2/DSI Data Streams to Parallel Data

Related Products

Related Applications


Newsletter Subscription

The Lattice Semiconductor CSI-2/DSI D-PHY Receiver IP Core converts DSI or CSI-2 data to 8-bit, 16-bit, 32-bit, or 64-bit data for Lattice FPGA devices built on the Lattice Avant™, Nexus™, and Nexus 2 platforms. The CSI-2/DSI D-PHY Receiver IP Core is intended for use in applications that require a D-PHY receiver in the FPGA logic. D-PHY Rx IP includes in both the high-speed and low power modules.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with MIPI D-PHY v1.2, MIPI DSI v1.1, and MIPI CSI-2 v1.2 specifications.
  • Selection between Hard Rx D-PHY or Soft Rx D-PHY implementation. Hard Rx D-PHY is only available for CrossLink-NX devices.
  • Supports MIPI DSI and MIPI CSI-2 interfaces up to 6 Gb/s for Soft D-PHY and up to 10 Gb/s for Hard D-PHY.
  • Supports 1, 2, 3, or 4 data lanes and one clock lane

Jump to

Block Diagram

CSI-2/DSI D-PHY Receiver

Ordering Information

The CSI-2 DSI D-PHY Receiver core is available for FREE for use in Diamond design software.

For Radiant design software, the CSI-2 DSI D-PHY Receiver core must be purchased:

  Part Number
Device Family Single Seat Annual Single Seat Perpetual
Certus-N2 DPHY-RX-CN2-US DPHY-RX-CN2-UT
Avant-G DPHY-RX-AVG-US DPHY-RX-AVG-UT
Avant-X DPHY-RX-AVX-US DPHY-RX-AVX-UT
Avant-E DPHY-RX-AVE-US DPHY-RX-AVE-UT
MachXO5-NX DPHY-RX-XO5-US DPHY-RX-XO5-UT
CertusPro-NX DPHY-RX-CPNX-US DPHY-RX-CPNX-UT
CrossLink-NX DPHY-RX-CNX-US DPHY-RX-CNX-UT
Certus-NX DPHY-RX-CTNX-US DPHY-RX-CTNX-UT
Bundled MIPI-BNDL-US MIPI-BNDL-UT

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CSI-2/D-PHY Receiver IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI2/DSI D-PHY Receiver IP Core User Guide for Diamond Design Software
FPGA-IPUG-02025 1.5 11/24/2021 PDF 1.3 MB
CSI-2/DSI D-PHY Receiver IP Core - User Guide
FPGA-IPUG-02081 2.4 6/26/2025 PDF 1.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Receiver IP Core - Release Notes
FPGA-RN-02040 1.1 6/26/2025 PDF 247.7 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW