Deinterlacer IP Core

4K Deinterlacing IP With Adaptive Motion Handling and Flexible Video Format Support

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The Lattice™ Semiconductor Deinterlacer IP core converts interlaced video into progressive video format using bob, intra motion and inter motion adaptive deinterlacing algorithms to reduce interline flickers and jagged edges. The Deinterlacer IP core supports image sizes up to 4k × 4k with YCbCr 4:2:2, 4:4:4 and RGB video formats. The Deinterlacer IP core supports dynamic parameter updating through a parameter bus, which can be configured to operate on a different clock from the core. Simple frame rate conversion is employed to support different input and output frame rates.

Latest Resource Utilization details are available in the IP Core User Guide.

Features:

  • Single color, YCbCr 4:2:2, YcbCr 4:4:4, and RGB video formats
  • Serial and parallel deinterlacing
  • Weave, bob, intra and inter motion adaptive deinterlacing algorithms
  • Frame rate conversion
  • Configurable initial field

Features

  • Supports for single color, YCbCr4:2:2, YcbCr4:4:4 and RGB video formats.
  • Supports serial and parallel deinterlacing.
  • Supports weave, bob, intra and inter motion adaptive deinterlacing algorithms.
  • Supports frame rate conversion.
  • Configurable initial field.
  • Configurable thresholds for inter motion adaptive deinterlacing algorithm.
  • Dynamic parameters updating: frame size, initial field and bypass mode.
  • Configurable parameter bus width.
  • Configurable separate parameters bus clock.
  • Configurable memory bus width and base address.
  • Configurable burst length and burst count.
  • Configurable internal FIFO type and depth.
  • Configurable pixel data width.
  • Configurable line buffer type.

Jump to

Block Diagram

Deinterlacer IP Core Deinterlacer Features

Ordering Information

The Deinterlacer IP is provided at no additional cost with the Lattice Radiant™ software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Deinterlacer IP Core - User Guide
FPGA-IPUG-02135 1.2 12/11/2025 PDF 692.4 KB
Deinterlacer IP Core User's Guide
IPUG97 1.1 9/24/2013 PDF 2.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Deinterlacer IP Core - Release Notes
FPGA-RN-02056 1.0 12/11/2025 PDF 239.7 KB

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