The Tri-Speed Ethernet (TSE) IP solution consists of the TSE IP Media Access Controller (MAC) core and the SGMII GbE Physical Coding Sublayer (SGMII PCS) IP core. The integration of TSE IP (MAC) core with the SGMII PCS IP core creates a seamless connection between MAC-level operations and physical Ethernet channels.
The TSE IP (MAC) is a complex core containing all the necessary logic, interfacing, and clocking infrastructure to integrate an external industry-standard Ethernet PHY with an internal processor efficiently and with minimal overhead.
The SGMII PCS IP core converts GMII frames into 8-bit code groups in both transmit and receive directions and performs auto-negotiation with a link partner as described in the Cisco SGMII and IEEE 802.3z specifications.
Resource Utilization details are available in the IP Core User Guide.