Description:
RISC V CPU instruction/data manager consists of exception handling routine in the BSP source: ..\src\bsp\driver\riscv_mc\interrupt.c
The API is a standard RISC V practice where it prints out the failure based on the mcause register when the RISC V instruction bus fetches an invalid instruction or reads from an invalid address.
You may observe UART terminal Printf hang during an exception handling event when esr_callback API is called.
Solution:
To workaround this issue, you will need to enable FIFO in Propel Builder UART IP, regenerate, and recompile your design. The Hello World template does not enable it by default.
Printf result after enable UART FIFO.
Exception caught: mcause=5 ,mepc=430, sp=1940
load access fault
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This issue is scheduled to be fixed in a future release version of Lattice Propel.