Video Library

This demo showcases a high-performance LTPI setup using a single System Control Module (SCM) connected to two Host Processor Modules (HPMs) via the Lattice MachXO3™ device. It demonstrates efficient aggregation of low-speed signals—GPIO, UART, and I2C—from the SCM to both HPMs, with real-time link status monitoring and environmental sensing. Each LTPI link operates independently, ensuring uninterrupted CPLD functionality even if one HPM disconnects.

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This demo highlights Lattice Semiconductor’s industry-first PQC-ready secure control FPGA, the Lattice MachXO5-NX 55TDQ, showcasing a single-chip solution that integrates attestation verifier, Platform Firmware Resiliency (PFR), and LTPI capabilities. Built on the power-efficient Lattice Nexus™ platform, the demo demonstrates robust post-quantum cryptography (PQC) support compliant with CNSA 2.0 and NIST standards, including ML-KEM and ML-DSA algorithms. It emphasizes crypto-agility, secure boot, hardware root of trust, and hybrid security models—making it ideal for datacenter, industrial, and communications infrastructure applications.

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This demo showcases Lattice Semiconductor’s implementation of the Modular Peripheral Sideband Tunneling Interface (MPESTI), a single-wire communication protocol developed under the Open Compute Project (OCP). It highlights seamless interoperability between a MPESTI Initiator and multiple target devices from Nuvoton and Renesas, connected via a fanout controller on the Lattice iCE40 UltraPlus™ board. The setup supports up to 64 endpoints, enables hot-plug capability, and eliminates the need for external MUX or switches—offering a scalable, cost-efficient solution for modular data center environments.

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The Onboarding LTPI Demo showcases Lattice’s seamless Plug and Play setup for Host Processor Module (HPM) endpoints using JSON-based onboarding. It highlights how LTPI bridges hardware differences between HPM and DC-SCM modules by combining I2C, UART, and GPIO into a unified high-speed interface. The demo features dynamic metadata capture, pre-link endpoint detection via a RISC-V I2C controller, and sensor interaction through a Raspberry Pi acting as a BMC—demonstrating scalable, interoperable integration for modern data center ecosystems.

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This demo showcases the establishment of a quantum-resistant secure communication channel using post-quantum cryptography (PQC) on the Lattice MachXO5™-55TDQ FPGA. It features ML-KEM for key exchange and ML-DSA for digital signing, simulating secure boot, mutual authentication, and encrypted data exchange over I2C. The setup includes pre-provisioned public keys, protection against impersonation and replay attacks, and aligns with SPDM 1.4 standards. Designed for crypto agility, the demo highlights Lattice’s commitment to future-proof firmware security in datacenter, industrial, and communications applications.

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The SEC-TPM Demo showcases a single-chip Root of Trust solution, integrating traditional TPM functionality with post-quantum cryptography (PQC) and Platform Firmware Resilience (PFR). Running on a RISC-V core, the demo highlights secure credential management anchored to hardware, leveraging Lattice’s RNG and crypto-agile architecture. It eliminates the need for external TPM chips, simplifying the supply chain and enabling secure remote updates—making it ideal for next-generation server security applications.

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This demo showcases Lattice’s unified security solution built on the Lattice MachXO5™-NX 55TDQ device, integrating attestation verifier, Platform Firmware Resilience (PFR), and LTPI capabilities into a single chip. Leveraging the Lattice Sentry™ 4.0 platform, it supports both traditional cryptography and post-quantum algorithms (ML-DSA, ML-KEM), enabling secure image authentication, key exchange, and encrypted communication. The solution is compliant with SPDM 1.2, NIST 800-193, and CNSA 2.0 standards, and offers robust connectivity via I2C, I3C, SMBus, and LTPI—delivering scalable, crypto-agile protection for modern server platforms.

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The SPDM 1.2 Demo showcases the Lattice Sentry™ 4.0 platform’s robust hardware and firmware security capabilities through cryptographic attestation. Running on the Lattice MachXO5™-NX 55TDQ device, the demo verifies device identity and firmware integrity using SPDM 1.2 commands over I2C and I3C interfaces, including LTPI channels. It highlights a modular framework designed for future security upgrades, including SPDM 1.4 and post-quantum cryptography (PQC) with ML-KEM and ML-DSA support—demonstrating Lattice’s commitment to evolving cybersecurity standards.

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The USB to I/O Conversion Demo showcases Lattice’s high-speed USB 2.0 connectivity solution built on the Lattice CrossLinkU™-NX FPGA, enabling seamless bridging between modern computing platforms and essential peripherals like GPIO, UART, and I2C. Supporting both CDC and MCTP USB classes, the demo highlights a scalable multi-endpoint architecture that manages up to three USB devices, ensuring robust system management and protocol flexibility. Designed for multi-node environments, this modular solution empowers developers with crypto-agile control and future-ready integration across industrial, embedded, and server applications.

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Experience a cutting-edge industrial human-machine interface (HMI) that features advanced operator attention sensing and identification. This demo enables seamless interaction with machinery, delivering real-time insights and precise control for enhanced operational efficiency.

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Learn the fundamentals of cybersecurity standards and regulations in this informative video. We break down the scope, key requirements, and essential security principles that organizations must follow to stay compliant and secure with leading agencies such as NIST, CISA, NSA, ENISA, ETSI, and the European Commission. Whether you're new to cybersecurity or looking to stay updated on regulatory expectations, this video provides a concise overview to help you navigate the landscape with confidence.

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As the low power programmable leader, Lattice is at the forefront of FPGA innovation. We're committed to delivering industry-leading low power, high-performance, small footprint solutions as a steadfast, trustworthy partner to our customers worldwide.

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The Lattice Nexus 2 platform offers significant improvements in power and performance efficiency, advanced connectivity, and leading security relative to the competition. The platform supports rapid development of multiple device families, enabling developers to create innovative products and address technical design challenges. Key features include multi-protocol SERDES with PCIe Gen4, up to 7.98 Gbps MIPI D & C-PHY, LPDDR4 interconnect, 2X programmable fabric speed, 2X DSP per logic, crypto agility, post-quantum readiness, and anti-tamper protection.

Lattice Radiant 2024.2 focuses on ease of use, new programming features and device support. We released version 2024.2 to support our newest device Certus-N2 in our new platform, Nexus 2.

Watch how the Lattice Nexus™ 2 FPGA platform delivers up to 3X lower power than similar class competitive devices, helping system and application engineers achieve power efficiency while simplifying thermal management and lowering operating costs.

Watch the incredible boot up speed of the Lattice Nexus™ 2 FPGA platform in this demonstration. With significantly faster boot up time compared to similar class competitive devices, the Lattice Nexus 2™ FPGA platform is designed to enable security and safety critical applications.

Watch how the Lattice Nexus™ 2 FPGA platform combines low power features and faster boot up capabilities to enable power constrained edge computing applications.

Watch how Lattice Avant™-X FPGAs run at up to 25Gbps on a SERDES eye diagram to deliver well defined logic levels, excellent signal integrity, and low power solutions for high speed serial protocols such as PCIe® and Ethernet.

Watch the mid-range Lattice Avant™-X FPGAs showcase their power efficiency leadership over similar class competitive devices, delivering solutions for power-constrained networking applications.

Watch the incredible boot up speed of the mid-range Lattice Avant™-G FPGAs in this demonstration. With a significantly faster boot-up time compared to similar class competitive devices, Lattice Avant-G FPGAs make them a go-to choice for security and safety-critical applications.

Watch as Glance by Mirametrix® enhances Industrial applications through a seamlessly integrated Industrial Human Machine Interface (HMI) from EXOR that undergoes face recognition, attention tracking, and gaze tracking to understand the region of focus for the user—improving safety and reducing human errors.

From Edge AI to cloud, demand for FPGAs is significantly growing thanks to their inherent programmability as developers look for more flexible and adaptable solutions. Watch the Lattice Developers Conference opening keynotes by Lattice executives to learn about the latest mid-range Lattice Avant™ FPGAs, expanded solution stacks, enhanced software capabilities, and how FPGAs help accelerate time-to-market and improve the longevity of product lifecycles.

Built on the award-winning Lattice Avant platform, the Avant-G and Avant-X FPGA families offer power efficiency, advanced connectivity, and optimized compute for mid-range applications across the Communications, Computing, Industrial, and Automotive markets.

Paving the road to the future, the Lattice Drive solution stack is Lattice's sixth application-specific solution stack that brings advanced Automotive application features to our customers looking for low power, scalable, flexible, and secure solutions to quickly develop innovative in-vehicle experiences.

Lattice Radiant is a full featured, easy-to-use FPGA design tool suite that’s all you need for FPGA design from synthesis through to verification. Download Radiant for free to explore more features!

As the low power programmable leader, Lattice is committed to delivering market-leading innovation to help our customers accelerate its application development and time-to-market. Our product and software portfolio growth and customer momentum are a testament to our mission.

Accton Technology CEO, Edgar Masri, shares his experience with Lattice’s power efficient FPGA technologies and his excitement around collaborations for Lattice Avant launch event.

NI Senior Vice President, Research & Development, Kevin Schultz, shares his experience with Lattice’s power efficient FPGA technologies and his excitement around collaborations for Lattice Avant launch event.

Rockwell Automation Senior Vice President, Intelligent Devices, Tessa Myers shares her experience with Lattice’s power efficient FPGA technologies and her excitement around collaborations for Lattice Avant launch event.

At Lattice, our ecosystem is strong and growing every day. Hear from our valued customers on their excitement around collaborations for Lattice Avant launch event.

Watch how the Lattice Avant FPGA platform provides scalable AI performance for Automotive applications. Lattice Avant FPGAs are designed to solve key customer challenges at the Edge by combining class-leading power efficiency, size and performance with an optimized feature set tailored to the needs of Edge applications like data processing and AI.

Watch how the Lattice Avant FPGA platform offers up to 2X faster throughput at lower power than similar class competitive devices and delivers increased bandwidth and reduces links, system cost and size, while enabling datapath applications.

Watch how the Lattice Avant FPGA platform delivers up to 2.5X lower power than similar class competitive devices, helping system and application engineers achieve power efficiency while simplifying thermal management and lowering operating costs.

Lattice is extending its low power leadership with the new Lattice Avant FPGA platform. Lattice Avant is a new FPGA platform purpose-built to bring our power efficient architecture, small size, and performance leadership to an expanded set of applications and help our customers unleash new levels of innovation

The Lattice Avant FPGA offers best-in-class power efficiency, advanced connectivity, and optimized compute that enable Lattice to address an expanded set of customer applications across the Communications, Computing, Industrial, and Automotive markets.

At Embedded World 2022, Lattice Head of R&D Steve Douglass delivered a keynote discussing the new ways to design more secure, flexible, and adaptable systems to address major technology trends in Edge Computing – accelerating compute requirements, expanding system features, increasing security threats, and faster time to market – to build even greater products.

Lattice Head of R&D Steve Douglass sat down with Editor-in-Chief of Design&Elektronik, Joachim Kroll at Embedded World Exhibition & Conference 2022 to discuss how FPGAs can solve many of the challenges developers face with today’s top technology trends, including mass connectivity and the rapid adoption of AI, as well as the rise in edge computing.

Lattice Nexus Platform is the industry’s first 28nm FD-SOI-based FPGA platform built with innovations at every level of design, from solutions, to architecture, to circuit, and delivers higher system performance at significantly reduced power consumption.

CrossLink-NX FPGA is the first family of FPGAs implemented on the new Lattice Nexus Platform. CrossLink-NX provides the energy efficiency, small form factor, high reliability and higher performance developers need to enable innovative embedded vision solutions for the Edge.

This demonstration measures the power consumption of Lattice’s CrossLink-NX FPGAs relative to other similar FPGAs using commercially available boards.

This demonstration measures the IO wakeup time of Lattice’s CrossLink-NX FPGAs relative to other similar FPGAs using commercially available development boards.

Lattice Semiconductor is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.

Lattice MachXO3D FPGA helps secure system components with a hardware root-of-trust. MachXO3D can protect, detect and recover other components from unauthorized firmware access at every stage of a system’s lifecycle, from the point of manufacturing all the way to the system’s end of life.

The full-featured Lattice sensAI stack includes everything developers need to evaluate, develop and deploy FPGA-based Machine Learning / Artificial Intelligence solutions - modular hardware platforms, example demonstrations, reference designs, neural network IP cores, software tools for development, and custom design services.

This video introduces the benefits of HDMI 2.1’s eARC feature:

• Higher bandwidth – 37M of audio that supports all audio formats
• Full home theater experience with the simplicity of operating a TV set
• Future proof receivers against changes in video standards

This demonstration takes the output from four fish-eye cameras and performs de-warping, white balance correction, and image stitching. The demonstration also enables the user to provides different views.

This demonstration identifies and tracks a human face. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.

This demonstration processes video images and identifies the presence of a human. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.

This demonstration tallies apples and oranges to demonstrate object counting. The inferencing is done using eight Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.

This demonstration looks for speed limit signs and interprets what is on the sign. The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA. Power consumption is less than 1W.

Learn how easy it is mix and match multiple I/O types with the modular VIP platform.

• Input options: HDMI, DisplayPort, Dual Sensor
• Output options: HDMI, DisplayPort, USB3-GbE

This video shows how you can use Lattice's CrossLink device to implement a MIPI DSI to LVDS bridge.

From always-on cameras with processing at the edge and the cloud to always-on displays and face detection, our FPGA-based solutions have you covered.

Taking a simple camera and converting it regular image into a 360 surround view doesn't have to be difficult. Learn how our CrossLink FPGA can help.

Our next-generation Lattice Radiant software is a full featured FPGA design tool suite. Achieve predictable FPGA design convergence, optimized for edge devices.

Learn how our Embedded Vision Development kit and 60 GHz WirelessHD products support autonomous robot requirements, such as collision avoidance, all while consuming an incredibly low amount of power.

HDMI 2.1 now includes a home theater feature called Enhanced Audio Return Channel (eARC), which will ensure forward compatibility between audio devices such as a Sound Bar, A/V Receiver (AVR) and TV.

Check out how CrossLink's collection of IP cores helps you solve design challenges with MIPI interface adoption.

We have combined the bridging capability of our CrossLink FPGA, the low-power, small form factor ECP5 and the high-resolution benefits of our HDMI ASSP, onto this modular platform. Learn about the specs of this development kit and let us help you enable flexible connectivity and energy efficient image processing for robotics, drones, ADAS, smart surveillance and AR/VR systems.

Lattice Semiconductor showcases product solutions for connectivity and processing at the edge.

Learn more about Lattice's CrossLink FPGA and its new 4:1 MIPI CSI-2 camera aggregator bridge, ideal for drones, AR/VR, 360 cameras, and other automotive and industrial solutions.

Learn how Lattice products support edge computing applications (video processing acceleration), sensor bridging for machine vision, and stereo vision for robotics and drones.

Learn how FPGAs can support the needs of modern Advanced Driver Assistance Systems (ADAS) .

Lattice CrossLink FPGA, ECP5 FPGA and HDMI ASSP come together to provide one clean and efficient solution for video processing and delivery.

Using Lattice’s ECP5 FPGA device, we are able to take the images of multiple automotive cameras, stitch them together, and apply many enhancing/correcting benefits to output one final, clean image for the driver.

The iCE40 UltraPlus is the world’s smallest FPGAs with enhanced memory & DSPs for reduced system cost, lower power consumption & faster time-to-market. Our sensor data fusion with embedded RISC-V and multi-sensor aggregation demos show why iCE40 UltraPlus is a must for your next consumer device.

We are demonstrating video and audio signal aggregation in products using Lattice iCE40 FPGAs.

The iCE40 UltraPlus is the world’s smallest FPGAs with enhanced memory & DSPs for reduced system cost, lower power consumption & faster time-to-market. Our sensor data fusion with embedded RISC-V and multi-sensor aggregation demos show why iCE40 UltraPlus is a must for your next consumer device.

Meet iCE40 UltraPlus, the first iCE40 product supporting MIPI D-PHY with LP and HS modes. Learn about additional benefits, like driving a MIPI DSI display along with integrated SRAM memory for frame buffering, in this video.

Whenever the interface on a camera does not match that of the application processor, a bridge is required. A common application example is muxing or merging multiple MIPI CSI-2 image sensors and combining them to one MIPI CSI-2 output. The CrossLink solution is a camera aggregator used for drones, 360 cameras, action cameras, surveillance and augmented reality applications.

The ECP5 FPGA Family breaks the rule that all FPGAs should be the highest density, power hungry, and expensive. With a focus on compact, high volume applications, Lattice optimized the ECP5 architecture for low cost, small form factor and low power consumption. These characteristics make the ECP5 devices ideal for delivering programmable connectivity solutions to complement ASICs and ASSPs.

See an overview of the MachXO2 product family. Learn how MachXO2 lowers cost, lowers power and integrates system functionality, all in a small package. See how easy it is to start designing with MachXO2 devices with free design tools, IP trials & reference designs.

Check out how easy it is to add CrossLink IPs to your designs.