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    ID
    Family
    Category
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  • What are the pin location requirements when using an input clock to capture input data?
    202
    All FPGA
    Customer Board Design
    Layout Review
  • How to solve the issue of "ispVM System  doesn't detect  parallel port ISP Download Cable" ?
    209
    All FPGA
    Device Programming
    ispVM System
  • What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
    203
    All FPGA
    Customer Board Design
    Layout Review
  • Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?
    200
    All FPGA
    Implementation
    Timing Analysis
  • LatticeECP3/DDR3: How can I configure the DDR3 memory clock to double the reference frequency (1:2:1…
    2087
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • What is the behavior of the Platform Manager Analog inputs? Is the voltage comparator output a logic…
    2085
    Platform Manager
    PAC-Designer
    LogiBuilder
  • Do Lattice devices contain any Rare Earth materials as mandated by the US Department of Commerce…
    2089
    All Devices
    Reliability and Materials
    Device Materials
  • Diamond: Where can I find the driver for Lattice USB programming cable in Lattice Diamond ?
    2081
    All FPGA
    Device Programming
    Cables
  • LatticeECP3: How to effectively use secondary region clock in LatticeECP3 devices?
    2082
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • All FPGA: What is the initial logic level of a register after power-up?
    204
    All FPGA
    Architecture
    General Logic
  • Diamond: How to check the un-constrained connections in Lattice Diamond?
    2084
    All FPGA
    Implementation
    Timing Closure
  • Power Manger II: Can the POWR1220AT8 be used to monitor negative voltages?
    2040
    Power Manager II
    Architecture
    IO
  • XP2: Does ispVM Embedded support TAG memory operations with the XP2?
    2049
    LatticeXP2
    Device Programming
    ispVM Embedded
  • LatticeXP2: Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?
    2043
    LatticeXP2
    Architecture
    Configuration/Programming
  • LatticeECP3: How to place DDR3 interface pins to minimize the SSO impact?
    2041
    LatticeECP3
    Lattice IP/Reference Design
    DDR3 SDRAM Controller
  • [ispMACH 4000]: I have 75 5V inputs to an ispMACH 4000 device. Which I/O type should I use between…
    2045
    ispMACH 4000
    Architecture
    IO
  • Power Manager II:  How much undershoot on the SDA pin can a POWR1220AT8 device endure without…
    2038
    Power Manager II
    Architecture
    I2C
  • ispLEVER: Using the command line, is there a command to directly convert .JED to .VME?
    2034
    All Devices
    Device Programming
    ispVM System
  • PAC Designer: Why does the Fitter report show some Flip flops as TFF and others as DFF for my…
    2039
    Power Manager II
    PAC-Designer
    Compile/Fit
  • Is it possible to determine what functions an ispVME data file performs?
    2031
    All FPGA
    Device Programming
    ispVM Embedded
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