5G Open RAN

The Advent of 5G ushers in a new era of ultra-large scale connectivity to accommodate IoT, significant bandwidth increases to meet the exponential growth of social media, streaming and gaming services, and low latency support for delay sensitive applications such as autonomous vehicle control and commercial drone applications.

To satisfy all of the use cases, more sophisticated design architectures are deployed within the Radio Unit (RU) and Distribution Unit (DU) .This, in turn, results in the need to manage more components on control paths and attention to power and thermal requirements of the system is critical.

In addition, board security is an important consideration as carriers are increasingly scrutinizing the integrity of equipment to defend against malicious attacks designed to incapacitate the network.

Lattice FPGA solutions provide:

  • Highly scalable PLD solution to meet all control needs
  • Best-in-Class security solutions to ensure protection of all boot functions and devices
  • Programmable to accommodate evolving 5G standards in the control plane

Jump to

Example Use Cases

O-RAN Split 7.2: RU Hardware Management Use Case

  • Precision power management and sequencing
  • Accurate temperature monitoring
  • Fault logging to efficiently identify HW faults
  • Reduced routing congestion and BOM

O-RAN Split 7.2: DU Platform Security Use Case

  • Protection for all firmware and critical data on board
  • Cryptography detect corrupted platform firmware at power on and all systems updates
  • Recover corrupted firmware and critical data to known good state

5G RAN DU Polar Code Use Case

  • Compliant with 3GPP 5G TS 38212 V15.7.0
  • Support for successive cancelation algorithm
  • Support for Code block lengths of 32,64,128, 256,512 and 1024
  • Support CRC6, CRC11, CRC24

Reference Designs

I2C从动软核

Reference Design

I2C从动软核

使用Verilog实现软核I2C从动,支持多款莱迪思FPGA系列
I2C从动软核
I2C总线主控软核

Reference Design

I2C总线主控软核

使用Verilog实现软核I2C总线主控,支持多款莱迪思FPGA系列
I2C总线主控软核
I2C (Inter-Integrated Circuit) 主控- WISHBONE兼容

Reference Design

I2C总线主控

Reference Design

I2C总线主控

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
I2C总线主控

IP Cores

Demo

拥有故障记录功能的电源时序演示

Demo

拥有故障记录功能的电源时序演示

使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。
拥有故障记录功能的电源时序演示

Support

技术支持

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