Article Details

ID: 2095
Case Type: faq
Category: Architecture
Related To: Memory EBR/Distributed
Family: All FPGA

Search Answer Database

Search Text Image

LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?

The Big/Little Endian mode switch will affect the word order when read data bus width and write data bus width are set as different values:



  • Case 1: write data bus width is 36bits and read data bus width is 18bits


    • For the Big Endian mode: if write Data[35:0], you will first read out Data[17:0] and then Data[38:18].

    • For the Little Endian mode: if write Data[35:0], you will first read out Data[35:18] and then Data[17:0].

  • Case 2: write data bus width is 18bits, and read data bus width is 36bits:


    • For the Big Endian mode, first word written into FIFO is shown at Q[17:0] when read out.

    • For the Little Endian mode, first word written into FIFO is shown at Q[35:18] when read out.