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  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • Object Counting

    Reference Design

    Object Counting

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • CSI-2/DSI D-PHY Receiver

    IP Core

  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
  • FPD-LINK Transmitter

    IP Core

    FPD-LINK Transmitter

    Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
    FPD-LINK Transmitter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Reference Design

    MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Modular MIPI/D-PHY Reference Design - Converts MIPI CSI-2 input to Parallel data type output
    MIPI DSI/CSI-2 to Parallel Bridge Reference Design
  • Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Reference Design

    Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Modular MIPI/D-PHY Reference Design - Converts Parallel data type input to MIPI CSI-2 output
    Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
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