The Lattice SPI Controller IP Core allows the host inside the FPGA to communicate with multiple external SPI Target devices.
The data size of the SPI transaction can be configured to 8, 16, 24, or 32 bits. This IP is designed to use an internal FIFO of configurable depth to minimize the host intervention during data transfer. The SPI Controller IP Core supports all SPI clocking modes — combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) to match the settings of external devices.
Latest Resource Utilization details are available in the IP Core User Guide.