LPDDR2 SDRAM Controller Lite IP Core

JESD209-2B General-purpose Memory Controller

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The Lattice Low Power Double Data Rate Type 2 (LPDDR2) Synchronous Dynamic Random-Access Memory (SDRAM) Controller Lite IP Core is a general-purpose memory controller that interfaces with industry standard LPDDR2 memory devices compliant with JESD209-2B, LPDDR2 SDRAM Standard, and provides a generic command interface to user applications.

LPDDR2 SDRAM is the next-generation Low Power SDRAM memory technology which offers a higher data rate, higher density, greater bandwidth and power efficiency. This core reduces the effort required to integrate the LPDDR2 memory controller with the user application design and minimizes the need to directly deal with the LPDDR2 memory interface.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Interfaces to industry standard LPDDR2 SDRAM components and modules compliant with JESD209-2B, LPDDR2 SDRAM Standard
  • Interfaces to LPDDR2 SDRAM at speeds up to 400 MHz/800 Mbps
  • Supports memory data path width of 16
  • Supports x16 device configuration
  • Supports single rank of an LPDDR2 device (one chip select)

Note: This “Lite” version IP only supports features and commands that LPDDR2 have in common with LPDDR3. This means burst lengths of 8 is supported, but 4 and 16 are not. Also, flash memory commands (LPDDR2-N) are not supported.

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Block Diagram

LPDDR2-SDRAM-Controller-Lite

Performance and Size

ECP51
Parameters Slices LUTs Registers I/O2 fMAX (MHz)3
Data Bus Width: 16 (x16) 1599 2241 1639 34 400 MHz (800 Mbps)
Data Bus Width: 32 (x32) 1818 2462 1937 54 400 MHz (800 Mbps)

1. Performance and utilization data are generated targeting an LFE5UM-85F-8BG756CES device using Lattice Diamond 3.10 design software with an LFE5UM control pack. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
2. Numbers shown in the I/O column represent the number of primary I/Os at the LPDDR2 memory interface. User interface (local side) I/Os are not included.
3. The LPDDR2 IP core can operate at 400 MHz (800 LPDDR2) in the fastest speed-grade (-8) when the data width is 32 bits or less and one chip select is used.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CertusPro-NX LPDDR2L-CPNX-UT LPDDR2L-CPNX-US
Certus-NX LPDDR2L-CTNX-UT LPDDR2L-CTNX-US
CrossLink-NX LPDDR2L-CNX-UT LPDDR2L-CNX-US
ECP5 LPDDR2L-E5-UT LPDDR2L-E5-US

IP Version: 1.0

Evaluate: To download a full evaluation version of this IP, go to the Clarity Designer tool and click the Lattice IP Server tab in the window. All LatticeCORE IP cores and modules available for download will be visible.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LPDDR2 SDRAM Controller Lite IP Core User Guide
FPGA-IPUG-02046 1.2 7/7/2021 PDF 1.4 MB
LPDDR2 SDRAM Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02089 1.6 12/21/2025 PDF 1.1 MB

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