I2C Controller IP Core

Flexible I2C Bus Control with Customizable FPGA-Based I2C Controller IP

Related Products

Related Applications

Lattice Semiconductor general-purpose I2C Controller IP offers an effective way to control an I2C bus. The programmable nature of FPGA provides you with flexibility of configuring the I2C Controller device to your need, thus allowing you to customize the I2C Controller to meet your specific design requirement.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports 7-bit and 10-bit Addressing Mode.
  • Programmable SCL frequency, supporting the following bus speeds:
    • Standard-mode (Sm) – up to 100 kbit/s
    • Fast-mode (Fm) – up to 400 kbit/s
    • Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up
  • Integrated Glitch filter

Block Diagram

I2C Controller IP Core Block DiagramExpand Image

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I2C Controller IP Core - User Guide
FPGA-IPUG-02071 2.1 12/11/2025 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I2C Controller IP Core - Release Notes
FPGA-RN-02027 1.2 12/11/2025 PDF 286.9 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW