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  •  syn1588® 多功能 IP Dual - 完全集成的双端口时钟同步解决方案

    IP Core

    syn1588® 多功能 IP Dual - 完全集成的双端口时钟同步解决方案

    A versatile IEEE1588 2-port PTP node. Each port may operate in any PTP role using either the default, the power, or the telecom profile.
  • 1:2 MIPI DSI显示接口带宽降低器

    IP Core

    1:2 MIPI DSI显示接口带宽降低器

    针对低分辨率显示器与高带宽应用处理器的互连,可以通过将输入连到多个显示器来降低带宽。莱迪思的1:2 MIPI DSI显示接口带宽降低器IP可帮助用户解决这些接口问题。
  • 10Gb+以太网MAC

    IP Core

    10Gb+以太网MAC

    Transmits and receives data between a host processor and an Ethernet network, compliant to IEEE 802.3-2005 standard
  • 10Gb以太网PCS

    IP Core

    10Gb以太网PCS

    Archived IP Core supporting ORCA FPGAs - For reference only.
     
  • 12V 热插拔控制

    Reference Design

    12V 热插拔控制

    Demonstrates how a Power Manager II ispPAC-POWR1220AT8 can be used to implement the functions required for +12V hot-swap applications
  • 1553编码器/解码器

    Reference Design

    1553编码器/解码器

    Implements Manchester II encoding and decoding required by the 1553 along with synchronization pattern insertion and identification.
     
  • 1进1出的MIPI CSI-2摄像头中继桥接

    IP Core

    1进1出的MIPI CSI-2摄像头中继桥接

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Used as a repeater to extend the length between the camera and the host processor.
  • 1进2出的MIPI CSI-2摄像头分离器桥接

    IP Core

    1进2出的MIPI CSI-2摄像头分离器桥接

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Connects to two cameras from a single application processor port.
  • 2.5Gbps以太网MAC IP核

    IP Core

    2.5Gbps以太网MAC IP核

    Transmits and receives data between a client application and an Ethernet network as specified in the 802.3 IEEE standard
  • 2.5Gbps以太网PCS IP核

    IP Core

    2.5Gbps以太网PCS IP核

    Implements the state machine functions for the physical coding sublayer (PCS) described in the IEEE 802.3z (1000BaseX) specification.
  • 2D FIR 滤波器IP核

    IP Core

    2D FIR 滤波器IP核

    Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory
  • 2D图像缩放IP核

    IP Core

    2D图像缩放IP核

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
  • 2D边沿检测器IP核

    IP Core

    2D边沿检测器IP核

    Detects edges in incoming video frames using the Sobel or Prewitt algorithms.
  • 32位PCI主控/目标

    IP Core

    32位PCI主控/目标

    Provides a customizable 32/64-bit master/target or target solution - revision 2.2 for speeds up to 66MHz
  • 32位PCI目标

    IP Core

    32位PCI目标

    Fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz
  • 3D深度测绘

    Demo

    3D深度测绘

    Determines the distance between an embedded device and an object using a Semi-Global Block Matching (SGBM) algorithm to determine 64 different disparity levels
  • 4进1出的MIPI CSI-2摄像头聚合桥接

    IP Core

    4进1出的MIPI CSI-2摄像头聚合桥接

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Aggregates multiple MIPI CSI-2 image sensor data to a single CSI-2 output.
  • 5V和3.3V热插拔控制器

    Reference Design

    5V和3.3V热插拔控制器

    Implements a hot swap controller design within a Power Manager II mixed-signal PLD
  • 64 位 PCI 目标

    IP Core

    64 位 PCI 目标

    Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit.
  • 64位PCI主控/目标

    IP Core

    64位PCI主控/目标

    Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit master/target or target solution
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