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ID: 1076
Case Type: faq
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Family: All FPGA

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How many DDR memory interfaces can be implemented on a single part?

The ECP2 and XP2 have 2 DQSDLLs one on each side of the device which are used compensate for DQS delays. Hence you can have up to 2 different interfaces running at different speeds on a single device.

If you need more than one DDR memory interface in one side, you can have them as long as the following conditions are met:
a. All DDR memory interfaces on the same side use the same reference clock source.
b. All DDR memory interfaces on the same side share the DQSDLL resource dedicated to the selected side.
c. The total number of DQ/DQS pads does not exceed the device limit for the selected side
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