Lattice Solutions

Everything you need to quickly and easily complete your design

Solution Type

Device Support












Tags



























































Providers

  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • SPI Slave to PWM Generation

    Reference Design

    SPI Slave to PWM Generation

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation
  • MachXO2 I2C Embedded Programming Access Firmware

    Reference Design

    MachXO2 I2C Embedded Programming Access Firmware

    Provides C code for interfacing to MachXO2 from a microcontroller, and RTL for implementing I2C between an external master and the MachXO2
    MachXO2 I2C Embedded Programming Access Firmware
  • Local Interconnect Network (LIN)

    IP Core

    Local Interconnect Network (LIN)

    Transmits and receives complete LIN frames to perform serial communication according to the LIN protocol specification
    LIN 
    Local Interconnect Network (LIN)
  • UART - WISHBONE Compatible

    Reference Design

    UART - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART - WISHBONE Compatible
  • SDR SDRAM Controller - Advanced

    Reference Design

    SDR SDRAM Controller - Advanced

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller - Advanced
  • CAN-CTRL

    IP Core

    CAN-CTRL

    Compliant to CAN 2.0 and CAN FD (ISO 11898-1.2015). Similar to Philips SJA1000 - error analysis, diagnosis, system maintenance, and optimization features.
    CAN-CTRL
  • Cyclic Redundancy Check

    Reference Design

    Cyclic Redundancy Check

    Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64
    Cyclic Redundancy Check
  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - Multiple Port Linker (BSCAN2)
  • I2C Bus Controller for Serial EEPROMs

    Reference Design

    I2C Bus Controller for Serial EEPROMs

    Provides an interface between standard microprocessors and I2C Serial EEPROM devices
    I2C Bus Controller for Serial EEPROMs
  • LED/OLED Driver

    Reference Design

    LED/OLED Driver

    Drive an LED via WISHBONE bus. Default is targeted to a GM1WA55311A LED but can be used to control other LEDs or OLEDs with similar functions.
    LED/OLED Driver
  • MIPI CSI-2 Receive Bridge

    Reference Design

    MIPI CSI-2 Receive Bridge

    Enables a mobile CSI-2 (Camera Serial Interface) image sensor to interface to an embedded Image Signal Processor. Up to 4 lanes at 900 Mbps per lane
    MIPI CSI-2 Receive Bridge
  • MIPI CSI-2 Transmit Bridge

    Reference Design

    MIPI CSI-2 Transmit Bridge

    Enables bridging of image inputs like subLVDS or HiSPI to MIPI CSI-2. Up to 4 lanes at 900 Mbps per lane
    MIPI CSI-2 Transmit Bridge
  • MIPI DSI Receive Bridge

    Reference Design

    MIPI DSI Receive Bridge

    Allows an AP (Application Processor) or other DSI source to interface to a non-DSI (such as LVDS) display. Up to 4 data lanes at 900 Mbps per lane
    MIPI DSI Receive Bridge
  • SPI Controller - WISHBONE Compatible

    Reference Design

    SPI Controller - WISHBONE Compatible

    Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.
    SPI Controller - WISHBONE Compatible
  • SPI Slave Peripheral using Embedded Function Block

    Reference Design

    SPI Slave Peripheral using Embedded Function Block

    Implements intuitive interface between an external SPI master and the XO2 internal registers (user logic) or memory extension in XO2.
    SPI Slave Peripheral using Embedded Function Block
  • Page 1 of 3
    First Previous
    1 2 3
    Next Last
    Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.