Lattice Solutions

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  • Byte to Pixel Converter

    IP Core

    Byte to Pixel Converter

    Modular MIPI/D-PHY IP - Converts Parallel Data From a D-PHY Receiver into Pixel Format
    Byte to Pixel Converter
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • CSI-2/DSI D-PHY Transmitter

    IP Core

    CSI-2/DSI D-PHY Transmitter

    Modular MIPI/D-PHY IP - PHY for transmitting MIPI CSI-2/DSI Data. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Transmitter
  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
  • FPD-LINK Transmitter

    IP Core

    FPD-LINK Transmitter

    Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
    FPD-LINK Transmitter
  • Pixel to Byte Converter

    IP Core

    Pixel to Byte Converter

    Modular MIPI/D-PHY IP - Converts Pixel Format Data to Parallel Byte Format
    Pixel to Byte Converter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • 1 to N MIPI CSI-2/DSI Duplicator

    Reference Design

    1 to N MIPI CSI-2/DSI Duplicator

    Modular MIPI/D-PHY Reference Design - Duplicate one MIPI CSI-2 channel to N DSI channels
    1 to N MIPI CSI-2/DSI Duplicator
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

    MIPI CSI-2 Virtual Channel Aggregation

    Modular MIPI/D-PHY Reference Design - Adaptable and flexible solution combines multiple MIPI CSI-2 inputs to a single CSI-2 output stream.
    MIPI CSI-2 Virtual Channel Aggregation
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Modular MIPI/D-PHY Reference Design - Aggregate multiple MIPI CSI-2 inputs up to 5 channels horizontally line by line to a single CSI-2 output
    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
  • SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Pixel to Byte Converter, SubLVDS Image Sensor Recevier and CSI-2/DSI D-PHY Transmitter
    SubLVDS to MIPI CSI-2 Image Sensor Bridge
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • 1 Input to 1 Output MIPI CSI-2 Camera Repeater Bridge

    IP Core

    1 Input to 1 Output MIPI CSI-2 Camera Repeater Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Used as a repeater to extend the length between the camera and the host processor.
    1 Input to 1 Output MIPI CSI-2 Camera Repeater Bridge
  • 1 Input to 1 Output MIPI DSI Display Interface Bridge

    IP Core

    1 Input to 1 Output MIPI DSI Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. MIPI DSI to MIPI DSI pass through for updated DCS config, scaling / cropping, or as a redriver.
    1 Input to 1 Output MIPI DSI Display Interface Bridge
  • 1 Input to 2 Output MIPI CSI-2 Camera Splitter Bridge

    IP Core

    1 Input to 2 Output MIPI CSI-2 Camera Splitter Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Connects to two cameras from a single application processor port.
    1 Input to 2 Output MIPI CSI-2 Camera Splitter Bridge
  • 1 Input to 2 Output MIPI DSI Display Splitter Bridge

    IP Core

    1 Input to 2 Output MIPI DSI Display Splitter Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Expands the number of display interfaces supported by an Application Processor.
    1 Input to 2 Output MIPI DSI Display Splitter Bridge
  • 1:2 MIPI DSI Display Interface Bandwidth Reducer

    IP Core

    1:2 MIPI DSI Display Interface Bandwidth Reducer

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Bridges an input video stream into two streams or one lower-resolution stream.
    1:2 MIPI DSI Display Interface Bandwidth Reducer
  • 2 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge

    IP Core

    2 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Aggregates multiple MIPI CSI-2 image sensor data to a single CSI-2 output.
    2 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge
  • 4 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge

    IP Core

    4 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Aggregates multiple MIPI CSI-2 image sensor data to a single CSI-2 output.
    4 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge
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