Lattice Solutions

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  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • Local Interconnect Network (LIN)

    IP Core

    Local Interconnect Network (LIN)

    Transmits and receives complete LIN frames to perform serial communication according to the LIN protocol specification
    LIN 
    Local Interconnect Network (LIN)
  • UART - WISHBONE Compatible

    Reference Design

    UART - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART - WISHBONE Compatible
  • SDR SDRAM Controller - Advanced

    Reference Design

    SDR SDRAM Controller - Advanced

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller - Advanced
  • I2C Bus Controller for Serial EEPROMs

    Reference Design

    I2C Bus Controller for Serial EEPROMs

    Provides an interface between standard microprocessors and I2C Serial EEPROM devices
    I2C Bus Controller for Serial EEPROMs
  • LED/OLED Driver

    Reference Design

    LED/OLED Driver

    Drive an LED via WISHBONE bus. Default is targeted to a GM1WA55311A LED but can be used to control other LEDs or OLEDs with similar functions.
    LED/OLED Driver
  • MIPI CSI-2 Receive Bridge

    Reference Design

    MIPI CSI-2 Receive Bridge

    Enables a mobile CSI-2 (Camera Serial Interface) image sensor to interface to an embedded Image Signal Processor. Up to 4 lanes at 900 Mbps per lane
    MIPI CSI-2 Receive Bridge
  • MIPI CSI-2 Transmit Bridge

    Reference Design

    MIPI CSI-2 Transmit Bridge

    Enables bridging of image inputs like subLVDS or HiSPI to MIPI CSI-2. Up to 4 lanes at 900 Mbps per lane
    MIPI CSI-2 Transmit Bridge
  • MIPI DSI Receive Bridge

    Reference Design

    MIPI DSI Receive Bridge

    Allows an AP (Application Processor) or other DSI source to interface to a non-DSI (such as LVDS) display. Up to 4 data lanes at 900 Mbps per lane
    MIPI DSI Receive Bridge
  • SPI Controller - WISHBONE Compatible

    Reference Design

    SPI Controller - WISHBONE Compatible

    Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.
    SPI Controller - WISHBONE Compatible
  • SPI Slave Peripheral using Embedded Function Block

    Reference Design

    SPI Slave Peripheral using Embedded Function Block

    Implements intuitive interface between an external SPI master and the XO2 internal registers (user logic) or memory extension in XO2.
    SPI Slave Peripheral using Embedded Function Block
  • I2C Slave Peripheral using Embedded Function Block

    Reference Design

    I2C Slave Peripheral using Embedded Function Block

    Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
    I2C Slave Peripheral using Embedded Function Block
  • I2S Controller with WISHBONE Interface

    Reference Design

  • Read and Write Usercode

    Reference Design

    Read and Write Usercode

    Read or change a Usercode or User Electronic Signature (UES) through general I/O without reprogramming the entire on-device Flash or interrupting the system.
    Read and Write Usercode
  • Sony Sub-LVDS to MIPI CSI-2 Sensor Bridge

    Reference Design

    Sony Sub-LVDS to MIPI CSI-2 Sensor Bridge

    Bridges serial Sub-LVDS interface to MIPI CSI-2
    Sony Sub-LVDS to MIPI CSI-2 Sensor Bridge
  • 7:1 LVDS Video Interface for MachXO2/3 and ECP5

    Reference Design

    7:1 LVDS Video Interface for MachXO2/3 and ECP5

    Implements standard 7:1 LVDS interfaces using the FPGA I/O structure
    7:1 LVDS Video Interface for MachXO2/3 and ECP5
  • Lattice Mico8 Open, Free Soft Microcontroller

    IP Core

    Lattice Mico8 Open, Free Soft Microcontroller

    8-bit microcontroller primarilyi targeted to the MachXO2 and MachXO3 families, but portable to other FPGAs. Full 18-bit wide instruction set and 32 registers
    Lattice Mico8 Open, Free Soft Microcontroller
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