I2C Bus Master

Reference Design LogoThis reference design is intended to demonstrate how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device. With the flexibility that this I2C-Bus Master Controller offers, a designer can communicate with up to 128 different I2C slave devices operating in standard or fast mode with transactions ranging from 1 to 256 bytes. The user can also customize the VHDL code to meet their own specific requirements and thus reduce valuable CPLD/FPGA area while maintaining the speed performance they have come to expect from Lattice devices. This design conforms to the Philips I2C Bus Specification version 1.0.

 
I2C Bus Master Controller

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Performance and Size

Device Family Tested Devices* Performance I/O Pins Utilization Revision
ECP5™ 7 LFE5U-45F-6MG285C >33MHz 18 198 LUTs 5.8
LatticeECP3™ 1 LFE3-17EA-6FTN256C >33MHz 18 200 LUTs 5.8
MachXO3L™ 8 LCMXO3L-4300C-6BG256C >33MHz 18 204 LUTs(Verilog-LSE Source) 5.8
190 LUTs (Verilog-Syn Source) 5.8
200 LUTs (VHDL-LSE Source) 5.8
191 LUTs (VHDL-Syn Source) 5.8
MachXO2™ 2 LCMXO2-256HC-4TG100C >33MHz 18 191 LUTs 5.8
MachXO™ 3 LCMXO256C-3T100C >33MHz 18 192 LUTs 5.8
LatticeXP2™ 4 LFXP2-5E-5M132C >33MHz 18 201 LUTs 5.8
ispMACH® 4000ZE5 LC4256ZE-5TN144C >33MHz 18 154 LUTs 5.8
Platform Manager™ 6 LPTM10-1247-3TG128CES >33MHz 18 192 LUTs 5.8

1. Performance and utilization characteristics are generated using LFE3-17EA-6FTN256C with Lattice Diamond® 3.1 design software.
2. Performance and utilization characteristics are generated using LCMXO2-256HC-4TG100C with Lattice Diamond 3.1 design software with LSE (Lattice Synthesis Engine).
3. Performance and utilization characteristics are generated using LCMXO256C-3T100C with Lattice Diamond 3.1 design software with LSE.
4. Performance and utilization characteristics are generated using LFXP2-5E-5M132C with Lattice Diamond 3.1 design software.
5. Performance and utilization characteristics are generated using LC4256ZE-5TN144C with Lattice ispLEVER® Classic 1.4 software.
6. Performance and utilization characteristics are generated using LPTM10-1247-3TG128CES with Lattice Diamond 3.1 design software.
7. Performance and utilization characteristics are generated using LFE5U-45F-6MG285C with Lattice Diamond 3.1 design software with LSE.
8. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.1 design software with LSE and Synplify Pro®.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
i2C Master Controller Source Code for MachXO
7/1/2005 ZIP 6.3 MB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD1005 5.9 1/10/2015 ZIP 809.7 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD1005 5.8 3/6/2014 PDF 987.4 KB

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