Simple Sigma-Delta ADC

Analog using FPGAs

Reference Design LogoThe Simple Sigma-Delta Analog-to-Digital Converter Reference Design targets the implementation of an analog-to-digital converter in a Lattice CPLD or FPGA. This reference design supports the use of an external analog comparator device, or optionally an on-chip LVDS buffer in devices with differential LVDS input support. Implementing this reference design can eliminate the need for dedicated and expensive analog-to-digital circuits (ADC), power supply monitors, and/or transducers.

The design can be implemented with few logic resources and is flexible enough to meet a variety of applications. The Simple Sigma-Delta ADC is an excellent choice for monitoring various sensors and power rails of a system.

Jump to

Block Diagram

Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
ICE40UP5K-SG48I >75 MHz 13+1(VREF) 99 LUTs 1.0
LCMXO2-1200HC-6MG132CES >150 MHz 13+1(VREF) 62 LUTs 1.3
LCMXO2280C-5FT256C >150 MHz 13+1(VREF) 51 LUTs 1.3
LFXP2-5E-5FT256C >150 MHz 13+1(VREF) 66 LUTs 1.3

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
Simple Sigma-Delta ADC, Documentation
FPGA-RD-02047 1.6 1/30/2020 PDF 971 KB
Simple Sigma-Delta ADC - Source Code
1.5 9/26/2018 ZIP 1.5 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.