GPIO Expander

Reference Design LogoFor many applications, more general purpose I/O (GPIO) ports are required than those available on a microprocessor. This design provides a solution that uses a Lattice PLD as a GPIO Expander. It provides additional control (control signal and data output signal) and monitoring (input data signal) capabilities when the microprocessor has insufficient I/O ports. The design interfaces a microprocessor with a back-end device through a common timing specification.

 

Jump to

Block Diagram

Performance and Size

Tested Devices* Language Performance I/O Pins Design Size Revision
LCMXO640C-3T100C Verilog/VHDL >100 MHz 47 238/206 LUTs 1.2
LC4256ZE-5TN100C Verilog/VHDL >100 MHz 47 187/194 Macrocells 1.2
LFE3-17EA-6FTN256C Verilog/VHDL > 100 MHz 47 242/211 LUTs 1.3
LFXP2-5E-5TN144C Verilog/VHDL >100 MHz 47 277/274 LUTs 1.3
LPTM10-12107-3FTG208CES Verilog/VHDL >100 MHz 47 250/207 LUTs 1.2

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
GPIO Expander, Documentation
RD1065 1.3 4/12/2011 PDF 280.6 KB
GPIO Expander, Source Code
RD1065 1.3 4/12/2011 ZIP 195.5 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.