RISC-V MC CPU IP Core

RISC-V CPU for Micro-controller Applications

The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

The Timer submodule is a 64-bit real time counter, which compares a real-time register to another register to assert the timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The submodule registers are accessed by the processor core using a 32-bit AHB-L interface.

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel Builder software. It can be targeted to the CrossLink-NX and MachXO3D FPGA devices and implemented using the Lattice Radiant software or Lattice Diamond software Place and Route tool integrated with the Synplify Pro synthesis tool.

Features

  • RV32I instruction set (RV32C only valid when PFR_OPT is unchecked)
  • Five stages of pipelines
  • Support for the AHB-L bus standard for instruction/data port
  • Optional debug through GDB and OpenOCD
  • Optional Timer/PIC modules
  • Interrupt and exception handling with Machine mode in RISC-V privileged ISA Specification v1.10
Lattice Propel

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Small-sized RISC-V CPU IP Core- Lattice Propel Builder
FPGA-IPUG-02114 1.0 6/3/2020


Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.