ispClock

IF (time = money), THEN (use ispClock)

Time waits for no silicon – Why waste time with zero-delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts when ispClock devices can replace them all?

Even a stopped clock tells the right time twice a day – ispClock devices can be programmed in-system to generate multiple clock frequencies and drive clock nets with different signalling requirements.

Time stream compensation – Compensate for output differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signalling requirements – all while meeting stringent skew and jitter standards.

Features

  • Available in multiple formats: ispClock5600A for clock generation, ispClock5400D for differential clock distribution and ispClock5300S for single-ended clock distribution
  • Reduce board space – a single ispClock replaces multiple types of clock devices
  • Maximum cycle-cycle jitter 70 ps (peak-peak)
  • Maximum phase jitter 50 ps
  • Support multiple interface types including: LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL

Jump to

Family Table

ispClock Product Family Selector Guide

Feature ispClock5600A Family ispClock5400D Family ispClock5300S Family
Outputs 20 or 10 10 or 6 20, 16, 12, 8, or 4
Input Operating Frequency Range 8 to 400MHz 50 TO 400MHz 8 to 267MHz
Output Operating Frequency Range 4 to 400MHz 50 TO 400MHz 5 to 267MHz
VCO Operation 320 to 800MHz 400 TO 800MHz 160 to 400MHz
Spread Spectrum Compatibility Yes Yes Yes
Single-Ended Fan-out Buffer Interfaces LVTTL, LVCMOS, HSTL, eHSTL, SSTL None LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Single-Ended Clock Reference and Feedback Interfaces LVTTL, LVCMOS, SSTL, HSTL LVCMOS LVTTL, LVCMOS, HSTL, eHSTL, SSTL
Differential Fan-out Buffer Interfaces SSTL, HSTL, LVDS, LVPECL LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS None
Differential Clock Reference and Feedback Interfaces HSTL, SSTL, LVDS, LVPECL LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS LVDS, LVPECL, HSTL, SSTL
Type of PLL Feedback Internal/External Internal/External External
M, N Dividers Count from 1 to 40 None None
Number of V Dividers 5 4 3
V Divider Count Range 2 to 80 (in steps of 2) 2 to 16 (in powers of 2) 1 to 32 (in powers of 2)
Maximum Cycle-Cycle Jitter 70ps (peak-peak) 29ps (peak-peak) 70ps (peak-peak)
Maximum Period Jitter (RMS) 12ps 2.5ps 12ps
Maximum Phase Jitter (RMS) 50ps 6ps Typ. 50ps
Maximum Static Phase Offset -100ps to 200ps -5ps to 95ps -40ps to 100ps
Frequencies Generated 5 4 3
Programmable Phase Skew 156ps to 12ns 156ps to 12ns 156ps to 5ns
Programmable Time Skew None 0ps to 288ps None
Fan-out Buffer Mode No Yes Yes
Programmable Termination 40 to 70Ω & 20Ω Setting None 40 to 70Ω & 20Ω Setting

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