Convolutional Neural Network (CNN) Compact Accelerator IP

Implement Machine Learning Inferencing in mWs

Take advantage of the FPGA’s parallel processing capability to implement compact CNNs including binarized versions known as BNNs. This IP enables you to implement CNNs in the Lattice iCE40 UltraPlus FPGAs that have power consumption in the mW range.

This IP uses on-chip DSP resources of the iCE40 UltraPlus devices to implement CNNs. Eleven Embedded Block Ram (EBR) are used as working memory by the acceleration engine. Users can choose to use EBR or the larger Single Port Memory (SPRAM) blocks to store the weights and instructions used by the engine.

This IP is paired with the Lattice Neural Network Complier tool. The compiler takes networks developed in Caffe or TensorFlow, and allows compilation into instructions that can be run by the Accelerator IP.

  • Implement CNNs including BNNs in iCE40 UltraPlus using on-chip DSP and memory blocks
  • Implement deep learning with mW power consumption
  • Network weight and operation sequence stored in either EBR or SPRAM blocks
  • Adjust operations and network weights for different BNN functions without changing the FPGA RTL
Lattice sensAI

Jump to

Block Diagram

BNN Implementations

CNN Implementations

Performance and Size

iCE40 UltraPlus Performance and Resource Utilization1 for BNN Implementations
Memory Type BNN Blob Type Registers LUTs EBR SRAM clk Fmax 2 (MHz)
EBRAM +1/0 2025 2890 27 0 42.289
DUAL_SPRAM +1/0 1799 2435 11 2 39.700
SINGLE_SPRAM +1/0 2005 2904 11 1 44.789
SINGLE_SPRAM +1/-1 1989 2695 11 1 42.207

1. Performance may vary when using a different software version or targeting a different device density or speed grade.
2. Fmax is generated when the FPGA design only contains BNN Accelerator IP Core, these values may be reduced when user logic is added to the FPGA design.

iCE40 UltraPlus Performance and Resource Utilization1 for CNN Implementations
Memory Type CNN Blob Type Registers LUTs EBR SRAM clk Fmax 2 (MHz)
EBRAM +1/0 2025 2890 27 0 42.289
DUAL_SPRAM +1/0 1799 2435 11 2 39.700
SINGLE_SPRAM +1/0 2005 2904 11 1 44.789
SINGLE_SPRAM +1/-1 1989 2695 11 1 42.207

1. Performance may vary when using a different software version or targeting a different device density or speed grade.
2. Fmax is generated when the FPGA design only contains BNN Accelerator IP Core, these values may be reduced when user logic is added to the FPGA design.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Compact-CNN-Accelerator-IP-Core-User-Guide
FPGA-IPUG-02038 1.1 9/24/2018 PDF 898.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Compact CNN Accelerator IP Package
1.0 9/24/2018 ZIP 199.6 KB


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